Method and system for driving a light emitting device display

• US 9,330,598 B2
• Filed: 09/09/2014
• Issued: 05/03/2016
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Nathan, Arokia, Chaji, Gholamreza
• Primary Examiner(s): Olson, Jason
• Assistant Examiner(s): Abebe, Sosina
• Application Number:
  US14/481,370
• Publication Number:
  US 20140375705A1
• Time in Patent Office: 602 Days
• Field of Search: 345/77, 345/212, 345/694
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0216 Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element

Abstract

A method and system for driving a light emitting device display is provided. The system provides a timing schedule which increases accuracy in the display. The system may provide the timing schedule by which an operation cycle is implemented consecutively in a group of rows. The system may provide the timing schedule by which an aging factor is used for a plurality of frames.

Claims

1. A display system comprising:

a pixel array including a plurality of pixel circuits arranged in rows and columns, each pixel circuit having a light emitting device, a capacitor, a drive transistor for driving the light emitting device, a first switch transistor connected to a data line for programming the pixel circuit during a programming operation to cause programming data from the data line to be stored in the capacitor, and a second switch transistor for generating a threshold voltage of the drive transistor during a generating threshold voltage operation; and

a driver configured to operate the second switch transistor to generate the threshold voltage of the drive transistor during the generating threshold voltage operation by operating the second switch transistor in a first pixel circuit in a first row of the pixel array while programming during the programming operation a second pixel circuit in a second row of the pixel array by operating the first switch transistor in the second pixel circuit, wherein the generating threshold voltage operation of the first pixel circuit has a duration greater than a row timing budget of the display system and pre-charges the first pixel circuit by resetting a node between the capacitor and a gate terminal of the drive transistor using an adjustable power supply to which the drive transistor is connected, wherein the pre-charging the first pixel circuit does not affect a data line associated with the first pixel circuit.

2. The display system as claimed in claim 1, wherein the driver is further configured to, after programming the second pixel circuit, program a third pixel circuit in a third row of the pixel array by operating the first switch transistor in the third pixel circuit while the generating threshold voltage operation is carried out in the first pixel circuit such that both the second pixel circuit and the third pixel circuit are programmed while the threshold voltage is generated in the first pixel circuit.

3. The display system as claimed in claim 1, wherein the first pixel circuit is pre-charged during a first phase of the generating threshold voltage operation, and by charging the threshold voltage of the respective drive transistors on the capacitor during a second phase of the generating threshold voltage operation, the second phase of the generating threshold voltage operation having a duration greater than a duration of the first phase.

4. The display system as claimed in claim 3,

wherein the adjustable power supply pre-charges the capacitor to a negative voltage in each of the plurality of pixel circuits during the first phase of the generating threshold voltage operation.

5. The display system as claimed in claim 1, wherein the first pixel circuit and the second pixel circuit share a data line of the pixel array, and wherein the generating threshold voltage operation is carried out in the first pixel circuit without affecting the data line such that the programming of the second pixel circuit is independent of the generating threshold voltage operation in the first pixel circuit.

6. The display system as claimed in claim 1, wherein the pixel array is divided into a plurality of segments each including a subset of the pixel circuits in the pixel array, and wherein the driver is further configured to implement the generating threshold voltage operation in a first segment of the plurality of segments while a second segment is programmed with display data or driven to emit light.

7. A display system as claimed in claim 1, wherein the plurality of pixel circuits are each configured with a gate terminal of the first switch transistor being connected to a first select line, the gate terminal of the second switch transistor being connected to a second select line, the first and second select lines being driven by the driver, the first terminal of the second switch transistor being connected to a gate terminal of the drive transistor, a first terminal of the first switch transistor being connected to the data line, a second terminal of the first switch transistor being connected to the gate terminal of the drive transistor, the data line being driven by the driver, the capacitor being connected between the gate terminal of the drive transistor and the light emitting device.

8. A display system as claimed in claim 1, wherein the plurality of pixel circuits are each configured with the capacitor being a first capacitor, each of the plurality of pixel circuits further including a second capacitor and a third switch transistor, and wherein the plurality of pixel circuits are each configured with a gate terminal of the first switch transistor being connected to a first select line, gate terminals of the second and third switch transistors being connected to a second select line, the first and second select lines being driven by the driver, a first terminal of the first switch transistor being connected to the data line, a second terminal of the first switch transistor being connected to the first and second capacitors, a first terminal of the second switch transistor being connected to the first and second capacitors, a first terminal of the third switch transistor being connected to the drive transistor and the light emitting device, a second terminal of the third switch transistor being connected to a gate terminal of the drive transistor, the first and second capacitors being connected to the gate terminal of the drive transistor in series.

9. The display system of claim 1, wherein the driver is further configured to operate the second switch transistor in a fourth row next to the first row of the pixel array to generate the threshold voltage of the drive transistor of the pixel circuit in the fourth row such that the generating threshold voltage operation of the drive transistor in the first row partially overlaps the generating threshold voltage operation of the drive transistor in the fourth row.

10. A method of driving a display, the display comprising a pixel array including a plurality of pixel circuits arranged in rows and columns, each pixel circuit having a light emitting device, a capacitor, a drive transistor for driving the light emitting device to emit light, a first switch transistor connected to a data line for programming the pixel circuit during a programming operation in which programming data from the data line is stored in the capacitor, and a second switch transistor for generating a threshold voltage of the drive transistor, the method comprising:

generating a threshold voltage of a drive transistor in a first pixel circuit in a first row of the pixel array by controlling a second switch transistor in the first pixel circuit to generate the threshold voltage during a generating threshold voltage operation without affecting a data line associated with the first pixel circuit; and

programming during the programming operation a second pixel circuit in a second row of the pixel array by controlling the first switch transistor in the second pixel circuit to program the second pixel circuit via the data line associated with the first pixel circuit, the programming being carried out while the threshold voltage of the first pixel circuit is being generated, and

wherein the generating the threshold voltage has a duration greater than a row timing budget of the display and wherein the generating the threshold voltage includes;

pre-charging the capacitor of the first pixel circuit with an initial voltage during a first phase to reset a voltage at the gate of the drive transistor, and

developing the threshold voltage of the drive transistor on the capacitor during a second phase by charging or discharging the initial voltage through the drive transistor, and

wherein the second phase has a duration greater than a programming timing budget of the display.

11. The method as claimed in claim 10, further comprising:

programming a third pixel circuit in a third row of the pixel array by operating a first switch transistor in the third pixel circuit to program the third pixel circuit via the data line associated with the first pixel circuit, the programming the third pixel circuit being carried out while the threshold voltage of the first pixel circuit is being generated such that both the second pixel circuit and the third pixel circuit are programmed while the threshold voltage is generated in the first pixel circuit.

12. The method as claimed in claim 10, wherein the generating the threshold voltage includes:

pre-charging a capacitor of the first pixel circuit with an initial voltage during a first phase, and

developing the threshold voltage of the drive transistor on the capacitor during a second phase by charging or discharging the initial voltage through the drive transistor, and

wherein the second phase has a duration greater than a programming timing budget of the display.

13. The method as claimed in claim 10, wherein the pre-charging is carried out by adjusting a voltage of a controllable power supply line.

14. The method as claimed in claim 10, wherein the pixel array is divided into a plurality of segments each including a subset of the plurality of pixel circuits in the pixel array, the pixel circuits in the first row of the pixel array being included in a first segment of the plurality of segments and pixel circuits in the second row of the pixel array being included in a second segment of the plurality of segments, and wherein the respective second switch transistors in the pixel circuits in the first segment are each controlled by a shared first global select line and the respective second switch transistors in the pixel circuits in the second segment are each controlled by a shared second global select line, and wherein the generating the threshold voltage of the first pixel circuit is carried out by operating the first global select line to simultaneously generate respective threshold voltages of the respective drive transistors in the plurality of pixel circuits in the first segment.

15. The method as claimed in claim 14, further comprising:

driving the plurality of pixels in the second segment to emit light while the generating the threshold voltages of the plurality of pixels in the first segment is carried out simultaneously.

16. A pixel circuit for a display, the pixel circuit including:

a light emitting device;

a drive transistor for driving the light emitting device by controlling the current flowing through the light emitting device;

a first and second capacitor coupled in series between a controllable power supply line and a gate terminal of the drive transistor, the controllable power supply line being coupled to a first terminal of the drive transistor, the second terminal of the drive transistor being coupled to the light emitting device;

a first switch transistor operated according to a first select line for programming the pixel circuit by coupling a data line to a node between the first and second capacitors, the first and second capacitors and the first switch transistor being connected to the node; and

a second switch transistor coupled to the gate terminal of the drive transistor for generating a threshold voltage of the drive transistor during a generating threshold voltage operation that precedes a programming operation wherein a programming voltage is provided on the data line, wherein during the programming operation the second switch transistor is off thereby charging the gate of the drive transistor to a voltage corresponding to at least the threshold voltage of the drive transistor and the programming voltage, wherein the second switch transistor is operated according to a global select line shared by a plurality of similar pixel circuits, the plurality of similar pixel circuits simultaneously generating threshold voltages of the respective drive transistors during the generating threshold voltage operation in the plurality of similar pixel circuits according to the global select line, the plurality of similar pixel circuits including pixel circuits in more than one row of the display.

17. The pixel circuit as claimed in claim 16, wherein the second switch transistor is coupled between the gate terminal of the drive transistor and the light emitting device, the second terminal of the drive transistor being coupled to the light emitting device.

18. The pixel circuit as claimed in claim 16, wherein the plurality of pixel circuits sharing the global select line is a subset of similar pixel circuits arranged in a pixel array having rows and columns, the pixel array being divided into a plurality of segments, each of the plurality of segments including a subset of the plurality of similar pixel circuits in more than one row of the pixel array, and wherein the second switch transistors in each segment of the plurality of segments are operated by global select lines shared by the pixel circuits in each segment.

19. The pixel circuit as claimed in claim 16, wherein the second switch transistor is coupled between the gate terminal of the drive transistor and a first terminal of the drive transistor, the second terminal of the drive transistor being connected to the light emitting device, the pixel circuit further comprising:

a third switch transistor coupled between the first terminal of the drive transistor and a power supply line.

20. The pixel circuit as claimed in claim 19, wherein the plurality of similar pixel circuits sharing the global select line to simultaneously generate threshold voltages includes pixel circuits from multiple rows and multiple columns of a pixel array.