Storage element, storage device, and signal processing circuit

• US 9,330,759 B2
• Filed: 05/04/2015
• Issued: 05/03/2016
• Est. Priority Date: 01/05/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohmaru, Takuro, Endo, Masami
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US14/702,817
• Publication Number:
  US 20150235700A1
• Time in Patent Office: 365 Days
• Field of Search: 327/208
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 99/22 including field-effect components
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Claims

1. A signal processing circuit comprising:

a register, the register comprising;

a first storage circuit; and

a second storage circuit, the second storage circuit comprising;

a capacitor comprising a pair of electrodes;

a first transistor; and

a second transistor,

wherein the first storage circuit is a volatile storage circuit,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein the second transistor comprises a channel formation region comprising a silicon,

wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit, and

wherein one of a source and a drain of the second transistor is electrically connected to the first storage circuit.

4. The signal processing circuit according to claim 1, wherein the oxide semiconductor material is an In—

Ga—

Zn-based oxide.

5. The signal processing circuit according to claim 1, wherein the oxide semiconductor material is an In—

Sn—

Zn-based oxide.

6. The signal processing circuit according to claim 1, wherein the first storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

7. The signal processing circuit according to claim 1, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first storage circuit.

8. The signal processing circuit according to claim 1, wherein the one of the source and the drain of the second transistor is electrically connected to an input terminal of the first storage circuit.

19. The signal processing circuit according to claim 1, wherein the first storage circuit is electrically connected to the gate of the second transistor and the one of the pair of electrodes through the first transistor.

2. A signal processing circuit comprising:

a register, the register comprising;

a first storage circuit; and

a second storage circuit, the second storage circuit comprising;

a capacitor comprising a pair of electrodes;

a first transistor;

a second transistor; and

a switch comprising a first terminal and a second terminal,

wherein the first storage circuit is a volatile storage circuit,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein the second transistor comprises a channel formation region comprising a silicon,

wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit,

wherein one of a source and a drain of the second transistor is electrically connected to the first terminal of the switch, and

wherein the second terminal of the switch is electrically connected to the first storage circuit.

9. The signal processing circuit according to claim 2, wherein the oxide semiconductor material is an In—

Ga—

Zn-based oxide.

10. The signal processing circuit according to claim 2, wherein the oxide semiconductor material is an In—

Sn—

Zn-based oxide.

11. The signal processing circuit according to claim 2, wherein the first storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

12. The signal processing circuit according to claim 2, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first storage circuit.

13. The signal processing circuit according to claim 2, wherein the second terminal of the switch is electrically connected to an input terminal of the first storage circuit.

3. A signal processing circuit comprising:

a register, the register comprising;

a first storage circuit; and

a second storage circuit, the second storage circuit comprising;

a capacitor comprising a pair of electrodes;

a first transistor;

a second transistor; and

a third transistor,

wherein the first storage circuit is a volatile storage circuit,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the first storage circuit.

14. The signal processing circuit according to claim 3, wherein the oxide semiconductor material is an In—

Ga—

Zn-based oxide.

15. The signal processing circuit according to claim 3, wherein the oxide semiconductor material is an In—

Sn—

Zn-based oxide.

16. The signal processing circuit according to claim 3, wherein the first storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

17. The signal processing circuit according to claim 3, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first storage circuit.

18. The signal processing circuit according to claim 3, wherein the other of the source and the drain of the third transistor is electrically connected to an input terminal of the first storage circuit.