Flash memory module and method for programming a page of flash memory cells

• US 9,330,767 B1
• Filed: 09/03/2013
• Issued: 05/03/2016
• Est. Priority Date: 08/26/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Steiner, Avi, Weingarten, Hanan
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huerta, Pablo
• Application Number:
  US14/017,112
• Time in Patent Office: 973 Days
• Field of Search: 365/185.19
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A flash memory module and a method for programming a page of flash memory cells, the method includes: receiving a cycle count indication indicative of a number of program cycles of the page of memory cells; setting a value of a programming parameter of a programming operation based on the cycle count indication; and programming at least one flash memory cell of the page of flash memory cells by performing the programming operation.

Claims

1. A method for programming a page of flash memory cells, the method comprises:

receiving a program and erase cycle count indication indicative of a number of program and erase cycles of the page of memory cells;

setting a value of a programming parameter of a programming operation based on the program and erase cycle count indication and on a type of the page;

wherein the type of the page comprises a least bit significant page and a most significant page;

wherein the setting of the value of the programming parameter of the programming operation is further based upon a non-uniformity of an actual distribution of threshold voltages of the page of flash memory cell; and

programming a flash memory cell of the page of flash memory cells by performing the programming operation.

2. The method according to claim 1, wherein the programming parameter is a value of a first programming pulse out of a sequence of programming pulses that are supplied to the flash memory cell during the programming operation of the flash memory cell.

3. The method according to claim 1, wherein the programming parameter is a target threshold voltage level of the flash memory cell at the end of the programming operation, the target threshold voltage represents a target logic value.

4. The method according to claim 3, wherein the setting comprises increasing a target threshold voltage level as a result of an increase in the number of program cycles.

5. The method according to claim 1, comprising generating the program and erase cycle count indication.

6. The method according to claim 1, wherein the programming parameter is a highest target voltage level of the flash memory cell.

7. The method according to claim 1 comprising setting different programming parameters to the different types of pages.

8. The method according to claim 7 wherein the different programming parameters are different sizes of a programming step, wherein programming step is a difference between values of consecutive pulses of a sequence of programming pulses that are supplied to the flash memory cell during the programming operation of the flash memory cell.

9. The method according to claim 1 wherein the programming parameters differ from an address of the flash memory cell.

10. The method according to claim 1 wherein the programming parameter is a size of a threshold voltage window that comprises multiple target voltage levels of a flash memory cell, the multiple target voltage levels represent multiple target logic values.

11. The method according to claim 1 wherein the setting of the value of the programming parameter of the programming operation is triggered in response to an non-uniformity of an actual distribution of threshold voltages of the page of flash memory cells.

12. The method according to claim 1 wherein the setting of the value of the programming parameter of the programming operation is further based upon an unevenness of distribution of errors between different target read threshold voltage levels of the flash memory cells of the page.

13. The method according to claim 1 wherein the setting of the value of the programming parameter of the programming operation is triggered in response to an unevenness of distribution of errors between different target read threshold voltage levels of the flash memory cells of the page.

14. A flash memory module;

comprising;

a flash memory unit that comprises at least one page of flash memory cells; and

a controller, for receiving a program and erase cycle count indication indicative of a number of program and erase cycles of the page of memory cells, for setting a value of a programming parameter of a programming operation based on the program and erase cycle count indication and on a type of the page;

wherein the type of the page comprises a least bit significant page and a most significant page;

wherein the setting of the value of the programming parameter of the programming operation is further based upon a non-uniformity of an actual distribution of threshold voltages of the page of flash memory cell; and

for programming a flash memory cell of the page of flash memory cells by performing the programming operation.

15. The flash memory module according to claim 14, wherein the programming parameter is a value of a first programming pulse voltage out of a sequence of programming pulses that are supplied to the flash memory cell during the programming operation of the flash memory cell.

16. The flash memory module according to claim 14, wherein the programming parameter is a target threshold voltage level of the flash memory cell at the end of the programming operation, the target threshold voltage represents a target logic value.

17. The flash memory module according to claim 14, wherein the controller is configured to generate the program and erase cycle count indication.

18. The flash memory module according to claim 14, wherein the programming parameter is a highest target voltage level of the flash memory cell.

19. The flash memory module according to claim 14 wherein the controller is arranged to set different programming parameters to the different types of pages.

20. The flash memory module according to claim 19 wherein the different programming parameters are different sizes of a programming step, wherein programming step is a difference between values of consecutive pulses of a sequence of programming pulses that are supplied to the flash memory cell during the programming operation of the flash memory cell.

21. The flash memory module according to claim 14 wherein the programming parameters differ from an address of the flash memory cell.

22. The flash memory module according to claim 14 wherein the programming parameter is a size of a threshold voltage window that comprises multiple target voltage levels of a flash memory cell, the multiple target voltage levels represent multiple target logic values.