Group word line erase and erase-verify methods for 3D non-volatile memory

• US 9,330,778 B2
• Filed: 10/27/2014
• Issued: 05/03/2016
• Est. Priority Date: 02/14/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Costa, Xiying, Mak, Alex, Alsmeier, Johann, Mui, Man L
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/524,153
• Publication Number:
  US 20150043278A1
• Time in Patent Office: 554 Days
• Field of Search: 365/185.22, 365/185.24
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

Claims

1. A method for performing an erase operation in a three-dimensional non-volatile memory device, comprising:

charging a channel of a string from one end of the string, the string comprises a plurality of storage elements and the channel extends through layers of the three-dimensional non-volatile memory device;

during the charging of the channel, setting one control gate voltage for one storage element of the plurality of storage elements to erase the one storage element, wherein the one control gate voltage is based on a distance of the one storage element from the one end of the string; and

performing an erase-verify test for the string by applying a common erase-verify control gate voltage to the plurality of storage elements while detecting a current through the string.

2. The method of claim 1, further comprising:

during the charging of the channel, setting the one control gate voltage for one group of adjacent storage elements of the plurality of storage elements to erase the one group of adjacent storage elements, wherein the one group of adjacent storage elements comprises the one storage element.

3. The method of claim 1, further comprising:

during the charging of the channel, setting another control gate voltage for another storage element of the plurality of storage elements to erase the another storage element, wherein the another control gate voltage is based on a distance of the another storage element from the one end of the string.

4. The method of claim 3, wherein:

the one control gate voltage is concurrent with the another control gate voltage.

5. The method of claim 3, further comprising:

during the charging of the channel, setting the another control gate voltage for another group of adjacent storage elements of the plurality of storage elements to erase the another group of adjacent storage elements, wherein the another group of adjacent storage elements comprises the another storage element.

6. The method of claim 3, wherein:

the distance of the one storage element from the one end of the string is greater than the distance of the another storage element from the one end of the string; and

the one control gate voltage is less than the another control gate voltage.

7. The method of claim 1, further comprising:

during the charging of the channel, setting the one control gate voltage for one group of adjacent storage elements of the plurality of storage elements which comprises the one storage element to erase the one group of adjacent storage elements, concurrent with setting another control gate voltage for another group of adjacent storage elements of the plurality of storage elements to erase the another group of adjacent storage elements; and

performing an erase-verify test for the one group of adjacent storage elements separately from performing an erase-verify test for the another group of adjacent storage elements.

8. The method of claim 7, wherein:

the erase operation comprises a plurality of erase-verify iterations;

the one group of adjacent storage elements is inhibited from further erasing in the erase operation when the one group of adjacent storage elements passes the erase-verify test for the one group; and

the another group of adjacent storage elements is inhibited from further erasing in the erase operation when the another group of adjacent storage elements passes the erase-verify test for the another group.

9. The method of claim 1, wherein:

the one control gate voltage is sufficiently low compared to a voltage in the channel to induce tunneling of holes from the channel into a charge trapping region of the one storage element.

10. A three-dimensional non-volatile memory device, comprising:

a string comprising a plurality of storage elements, the string comprises a channel which extends in a pillar, and the plurality of storage elements comprise one group of storage elements and another group of storage elements; and

a control circuit in communication with the string, the control circuit, to perform an erase operation for the string, is configured to;

charge the channel from one end of the string and concurrently set one control gate voltage for the one group of storage element to erase the one group of storage elements and set another control gate voltage for the another group of storage elements to erase the another group of storage elements, wherein the one control gate voltage is different than the another control gate voltage.

11. The three-dimensional non-volatile memory device of claim 10, wherein:

the one control gate voltage is based on a distance of the one group of storage elements from the one end of the string;

the another control gate voltage is based on a distance of the another group of storage elements from the one end of the string;

the distance of the one group of storage elements from the one end of the string is greater than the distance of the another group of storage elements from the one end of the string; and

the one control gate voltage is less than the another control gate voltage.

12. The three-dimensional non-volatile memory device of claim 10, wherein:

the control circuit is configured to apply the one control gate voltage concurrently with the another control gate voltage.

13. The three-dimensional non-volatile memory device of claim 10, wherein:

the channel is in a vertical memory hole.

14. A method for performing an erase operation in a three-dimensional non-volatile memory device, comprising:

charging a channel of a string, the string comprises a plurality of storage elements, and the channel extends in a vertical pillar; and

during the charging of the channel, setting control gate voltages for the plurality of storage elements to erase the plurality of storage elements; and

performing an erase-verify test separately for different groups of the storage elements.

15. The method of claim 14, wherein:

the control gate voltages comprise a common control gate voltage.

16. The method of claim 14, wherein:

the erase-verify test is performed in one erase-verify iteration of a plurality of erase-verify iterations of the erase operation;

a pass or fail status is set for each group of the different groups based on the erase-verify test in the one erase-verify iteration;

one or more groups of the different groups have the pass status and are inhibited from further erasing in a remainder of the erase operation; and

one or more groups of the different groups have the fail status and are further erased in a next erase-verify iteration of the plurality of erase-verify iterations.

17. The method of claim 14, wherein:

the control gate voltages are common within each group of the different groups and different in the different groups.

18. The method of claim 14, wherein:

the performing the erase-verify test comprises applying an erase-verify control gate voltage to storage elements of the string in one group of the different groups while applying a pass voltage to remaining storage elements of the string and detecting a current through the string, followed by applying the erase-verify control gate voltage to storage elements of the string in another group of the different groups while applying the pass voltage to remaining storage elements of the string and detecting a current through the string.

19. A three-dimensional non-volatile memory device, comprising:

a plurality of storage elements, the plurality of storage elements comprise a channel which extends in a vertical pillar; and

a control circuit in communication with the plurality of storage elements, the control circuit, to perform an erase operation for the plurality of storage elements, is configured to;

charge the channel, and

during the charging of the channel, set control gate voltages for the plurality of storage elements to erase the plurality of storage elements, and

perform an erase-verify test separately for each group of different groups of the storage elements.

20. The three-dimensional non-volatile memory device of claim 19, wherein:

the control gate voltages comprise a common control gate voltage.

21. The three-dimensional non-volatile memory device of claim 19, wherein:

the control gate voltages are common within each group of the different groups and different in the different groups.