DRAM-based anti-fuse cells
First Claim
1. An apparatus, comprising:
- a plurality of word lines;
a plurality of bit lines;
a cell plate;
a plurality of cells, wherein each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the bit lines and the cell plate, and wherein the switch is controlled by an associated one of the word lines; and
a control circuit configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the word lines is activated.
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Accused Products
Abstract
Apparatuses and methods for programming and reading from anti-fuse cells are disclosed herein. For example, a semiconductor device may include a plurality of word lines, a plurality of bit lines, a cell plate, a plurality of cells, and a control circuit. Each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the plurality of bit lines and the cell plate, and the switch is controlled by an associated one of the plurality of word lines. The control circuit is configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the plurality of word lines is activated.
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Citations
25 Claims
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1. An apparatus, comprising:
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a plurality of word lines; a plurality of bit lines; a cell plate; a plurality of cells, wherein each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the bit lines and the cell plate, and wherein the switch is controlled by an associated one of the word lines; and a control circuit configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the word lines is activated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus, comprising:
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a plurality of first word lines; a plurality of first bit lines; a first cell plate; a plurality of first cells, wherein each of the plurality of first cells includes a first switch and a first capacitor coupled in series between an associated one of the plurality of first bit lines and the first cell plate, and wherein the first switch is controlled by an associated one of the plurality of first word lines; a first control circuit configured to supply the first cell plate with a first voltage and maintain the first cell plate at the first voltage after one of the plurality of first word lines is activated; a plurality of second word lines; a plurality of second bit lines; a second cell plate; a plurality of second cells, wherein each of the plurality of second cells includes a second switch and a second capacitor coupled in series between an associated one of the plurality of second bit lines and the second cell plate, and wherein the second switch is controlled by an associated one of the plurality of second word lines; and a second control circuit configured to supply the second cell plate with the first voltage and change the second cell plate from the first voltage to a second voltage before one of the plurality of second word lines is activated. - View Dependent Claims (13, 14, 15)
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16. An apparatus, comprising:
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a first cell array that comprises; a plurality of first word lines; a plurality of first bit lines; a first cell plate; a plurality of first cells, wherein each of the plurality of first cells includes a first switch and a first capacitor coupled in series between an associated one of the plurality of first bit lines and the first cell plate, and wherein the first switch is controlled by an associated one of the plurality of first word lines, and wherein each of the plurality of first cells is configured to store data in accordance with an amount of charge stored on the first capacitor without deteriorating an electrical characteristic thereof; and a second cell array that comprises; a plurality of second word lines; a plurality of second bit lines; a second cell plate; a plurality of second cells, wherein each of the plurality of second cells includes a second switch and a second capacitor coupled in series between an associated one of the plurality of second bit lines and the second cell plate, and wherein the second switch is controlled by an associated one of the plurality of second word lines, and wherein each of the plurality of second cells is configured to store data in accordance with whether an electrical characteristic thereof has been deteriorated. - View Dependent Claims (17, 18, 19, 20)
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21. An apparatus, comprising:
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a plurality of anti-fuse cells, wherein one or more of the plurality of anti-fuse cells are programmed to store one of a low state and a high logic state, and wherein each of the plurality of anti-fuse cells includes a capacitor; and a controller coupled to the plurality of anti-fuse cells and configured to read the logic states stored in the plurality of anti-fuse cells, wherein the controller is configured to apply a first voltage to a first node of the capacitor and a second voltage to a second node of the capacitor during a first step of a command, and wherein the controller is further configured to alter the first voltage to a third voltage and decouple the second voltage from the second node of the capacitor during a second step of the command, wherein a voltage on the second node changes to the third voltage during the second step of the command. - View Dependent Claims (22, 23, 24, 25)
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Specification