DRAM-based anti-fuse cells

• US 9,330,794 B1
• Filed: 03/04/2015
• Issued: 05/03/2016
• Est. Priority Date: 03/04/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Miyatake, Shinichi
• Primary Examiner(s): Dinh, Son
• Application Number:
  US14/638,831
• Time in Patent Office: 426 Days
• Field of Search: 365/96, 365/149
• US Class Current: 1/1
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/783 with refresh of replacement cells, e.g. in DRAMs

Abstract

Apparatuses and methods for programming and reading from anti-fuse cells are disclosed herein. For example, a semiconductor device may include a plurality of word lines, a plurality of bit lines, a cell plate, a plurality of cells, and a control circuit. Each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the plurality of bit lines and the cell plate, and the switch is controlled by an associated one of the plurality of word lines. The control circuit is configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the plurality of word lines is activated.

Claims

1. An apparatus, comprising:

a plurality of word lines;

a plurality of bit lines;

a cell plate;

a plurality of cells, wherein each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the bit lines and the cell plate, and wherein the switch is controlled by an associated one of the word lines; and

a control circuit configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the word lines is activated.

2. The apparatus of claim 1, wherein the control circuit is configured to change the cell plate from the first voltage to the second voltage responsive to a first operation.

3. The apparatus of claim 2, wherein the control circuit is configured to change the cell plate from the second voltage to the first voltage after the one of the word lines is activated.

4. The apparatus of claim 3, wherein the control circuit is configured to supply the plurality of bit lines with a first state responsive to the first operation before the one of the word lines is activated.

5. The apparatus of claim 2, wherein the control circuit is configured to supply the cell plate with the first voltage and change the cell plate from the first voltage to a third voltage responsive to a second operation while one of the word lines is activated.

6. The apparatus of claim 5, further comprising:

a selector configured to receive the first to third voltages and provide one of the first to third voltages to the cell plate.

7. The apparatus of claim 6, wherein the selector is configured to provide the second voltage to the cell plate responsive to the first operation, and provide the third voltage to the cell plate responsive to the second operation.

8. The apparatus of claim 7, further comprising:

a voltage generator configured to receive a power supply voltage and generate the first to third voltages.

9. The apparatus of claim 8, wherein each of the first and second voltages is less in absolute value than the power supply voltage, and the third voltage is greater in absolute value than the power supply voltage.

10. The apparatus of claim 5, wherein the first operation is a read operation.

11. The apparatus of claim 10, wherein the second operation is a programming operation, and a capacitor of a selected cell is provided a voltage larger than a breakdown voltage of a dielectric of the capacitor.

12. An apparatus, comprising:

a plurality of first word lines;

a plurality of first bit lines;

a first cell plate;

a plurality of first cells, wherein each of the plurality of first cells includes a first switch and a first capacitor coupled in series between an associated one of the plurality of first bit lines and the first cell plate, and wherein the first switch is controlled by an associated one of the plurality of first word lines;

a first control circuit configured to supply the first cell plate with a first voltage and maintain the first cell plate at the first voltage after one of the plurality of first word lines is activated;

a plurality of second word lines;

a plurality of second bit lines;

a second cell plate;

a plurality of second cells, wherein each of the plurality of second cells includes a second switch and a second capacitor coupled in series between an associated one of the plurality of second bit lines and the second cell plate, and wherein the second switch is controlled by an associated one of the plurality of second word lines; and

a second control circuit configured to supply the second cell plate with the first voltage and change the second cell plate from the first voltage to a second voltage before one of the plurality of second word lines is activated.

13. The apparatus of claim 12, wherein each of the plurality of first and second cells is a dynamic random access memory cell.

14. The apparatus of claim 13, wherein each of the plurality of first cells functions as a volatile memory cell and each of the plurality of second cells functions as a nonvolatile memory cell.

15. The apparatus of claim 14, wherein a fault address corresponding to a fault cell of the plurality of first cells is held at some of the plurality of second cells.

16. An apparatus, comprising:

a first cell array that comprises;

a plurality of first word lines;

a plurality of first bit lines;

a first cell plate;

a plurality of first cells, wherein each of the plurality of first cells includes a first switch and a first capacitor coupled in series between an associated one of the plurality of first bit lines and the first cell plate, and wherein the first switch is controlled by an associated one of the plurality of first word lines, and

wherein each of the plurality of first cells is configured to store data in accordance with an amount of charge stored on the first capacitor without deteriorating an electrical characteristic thereof; and

a second cell array that comprises;

a plurality of second word lines;

a plurality of second bit lines;

a second cell plate;

a plurality of second cells, wherein each of the plurality of second cells includes a second switch and a second capacitor coupled in series between an associated one of the plurality of second bit lines and the second cell plate, and wherein the second switch is controlled by an associated one of the plurality of second word lines, and

wherein each of the plurality of second cells is configured to store data in accordance with whether an electrical characteristic thereof has been deteriorated.

17. The apparatus of claim 16, further comprising:

a control circuit configured to supply the second cell plate with a first voltage and change the second cell plate from the first voltage to a second voltage before one of the plurality of second word lines is activated.

18. The apparatus of claim 17, further comprising:

a selector configured to receive the first and second voltages and output one of the first and second voltages to the second cell plate responsive to a control signal from the control circuit.

19. The apparatus of claim 18, further comprising:

a voltage generator configured to receive a power supply voltage and generate the first and second voltages based thereon.

20. The apparatus of claim 19, wherein the first voltage is less in absolute value than the power supply voltage, and the second voltage is larger in absolute value than the power supply voltage.

21. An apparatus, comprising:

a plurality of anti-fuse cells, wherein one or more of the plurality of anti-fuse cells are programmed to store one of a low state and a high logic state, and wherein each of the plurality of anti-fuse cells includes a capacitor; and

a controller coupled to the plurality of anti-fuse cells and configured to read the logic states stored in the plurality of anti-fuse cells, wherein the controller is configured to apply a first voltage to a first node of the capacitor and a second voltage to a second node of the capacitor during a first step of a command, and wherein the controller is further configured to alter the first voltage to a third voltage and decouple the second voltage from the second node of the capacitor during a second step of the command, wherein a voltage on the second node changes to the third voltage during the second step of the command.

22. The apparatus of claim 21, wherein each of the plurality of anti-fuse cells comprises a switch coupled between the second node of respective capacitor and a bitline, wherein the switch is enabled during the first step of the command to provide the second voltage to the second node of the capacitor.

23. The apparatus of claim 22, wherein the switch is disabled during the second step of the command to decouple the second node of the capacitor from the bitline.

24. The apparatus of claim 21, wherein one or more of the plurality of anti-fuse cells are programmed by applying a voltage across a dielectric of their respective capacitors, wherein the voltage is greater than a breakdown voltage of the dielectric.

25. The apparatus of claim 21, wherein the plurality of anti-fuse cells comprise dynamic random access cells.