Integrated circuit structure with inductor in silicon interposer

• US 9,330,823 B1
• Filed: 12/19/2011
• Issued: 05/03/2016
• Est. Priority Date: 12/19/2011
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rahman, Arifur, Wu, Zhaoyin D., Kim, Namhoon
• Primary Examiner(s): Chan, Tsz
• Application Number:
  US13/329,832
• Time in Patent Office: 1,597 Days
• Field of Search: 336/200, 336/232, 257/531
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 5/00 Coils superconducting coils H01F6/06; fixed inductances of the signal type H01F17/00
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An integrated circuit structure can include an interposer having a plurality of conductive layers and a die coupled to the interposer through an internal interconnect structure. The integrated circuit structure can include an inductor implemented within at least one of the conductive layers of the interposer. The inductor can include a first terminal and a second terminal. The first terminal and the second terminal can be coupled to the internal interconnect structure.

Claims

1. An integrated circuit structure, comprising:

an interposer comprising a plurality of conductive layers, a first interconnect region that includes one or more of the plurality of conductive layers, a second interconnect region that includes one or more of the plurality of conductive layers, wherein the first interconnect region is separated from and coupled to the second interconnect region by a plurality of through silicon vias;

a first die coupled to the second interconnect region of the interposer through an internal interconnect structure; and

an inductor implemented within at least one of the conductive layers of the first interconnect region of the interposer and fully enclosed within the interposer;

wherein the inductor comprises a first terminal and a second terminal;

wherein the first terminal is coupled to the first die via the internal interconnect structure and the second terminal is coupled to the first die via the internal interconnect structure; and

wherein the interposer has a substrate resistivity that is higher than a substrate resistivity of the first die.

2. The integrated circuit structure of claim 1, wherein:

the first terminal of the inductor couples to a first node within the first die through the internal interconnect structure; and

the second terminal of the inductor couples to a second node within the first die through the internal interconnect structure.

3. The integrated circuit structure of claim 1, further comprising a second die coupled to the interposer, wherein:

the first terminal of the inductor couples to a first node within the first die through the internal interconnect structure; and

the second terminal of the inductor couples to a first node within the second die through the internal interconnect structure.

4. The integrated circuit structure of claim 1, wherein the plurality of conductive layers are implemented in layers of the interposer closest to the first die.

5. The integrated circuit structure of claim 1, wherein the plurality of conductive layers are implemented in layers of the interposer farthest from the first die.

6. The integrated circuit structure of claim 1, wherein the at least one of the conductive layers of the interposer used to implement the inductor has a thickness greater than a thickness of a conductive layer within the first die.

7. The integrated circuit structure of claim 1, wherein the first die is coupled to a first planar surface of the interposer through the internal interconnect structure, the integrated circuit structure further comprising:

a second die coupled to a second planar surface of the interposer through the internal interconnect structure;

wherein the first planar surface opposes, and is parallel to, the second planar surface;

wherein the first terminal couples to a first node located in the first die through the internal interconnect structure; and

wherein the second terminal couples to a second node located in the second die through the internal interconnect structure.

8. An integrated circuit structure, comprising:

an interposer comprising a plurality of conductive layers, a first interconnect region that includes one or more of the plurality of conductive layers, a second interconnect region that includes one or more of the plurality of conductive layers, wherein the first interconnect region is separated from and coupled to the second interconnect region by a plurality of through silicon vias;

a die coupled to a first planar surface of the second interconnect region of the interposer through an internal interconnect structure;

an external interconnect structure configured to couple a second planar surface of the interposer to nodes external to the integrated circuit structure; and

an inductor implemented within at least one of the conductive layers of the first interconnect region of the interposer and fully enclosed within the interposer;

wherein the inductor comprises a first terminal and a second terminal;

wherein the first terminal of the inductor and the second terminal of the inductor each is coupled only to the external interconnect structure; and

wherein circuitry external to the integrated circuit structure couples to the inductor without propagating signals through the die.

9. The integrated circuit structure of claim 8, wherein:

the external interconnect structure comprises a plurality of solder bumps;

the first terminal of the inductor couples to a first node external to the integrated circuit structure through a first solder-bump; and

the second terminal of the inductor couples to a second node external to the integrated circuit structure through a second solder-bump.

10. The integrated circuit structure of claim 8, wherein the plurality of conductive layers are implemented in layers of the interposer closest to the die.

11. The integrated circuit structure of claim 8, wherein the plurality of conductive layers are implemented in layers of the interposer farthest from the die.

12. The integrated circuit structure of claim 8, wherein the interposer has a substrate resistivity that is higher than a substrate resistivity of the die.

13. The integrated circuit structure of claim 8, wherein the at least one of the conductive layers of the interposer used to implement the inductor has a thickness greater than a thickness of a conductive layer within the die.

14. An integrated circuit structure, comprising:

an interposer comprising a plurality of conductive layers, a first interconnect region that includes one or more of the plurality of conductive layers, a second interconnect region that includes one or more of the plurality of conductive layers, wherein the first interconnect region is separated from and coupled to the second interconnect region by a plurality of through silicon vias;

a first die coupled to a first planar surface of the second interconnect region of the interposer through an internal interconnect structure;

an external interconnect structure configured to couple a second planar surface of the interposer circuitry external to the integrated circuit; and

an inductor implemented within at least one of the conductive layers of the first interconnect region of the interposer and fully enclosed within the interposer;

wherein the interposer has a substrate resistivity that is higher than a substrate resistivity of the first die;

wherein a first terminal of the inductor and a second terminal of the inductor each is coupled only to the external interconnect structure; and

wherein the circuitry external to the integrated circuit structure couples to the inductor without propagating signals through the first die.

15. The integrated circuit structure of claim 14, wherein the at least one of the conductive layers of the interposer used to implement the inductor has a thickness greater than a thickness of a conductive layer within the first die.

16. The integrated circuit structure of claim 14, wherein:

the first terminal couples to a first external node through the external interconnect structure; and

the second terminal couples to a second external node through the external interconnect structure.

17. The integrated circuit structure of claim 16, wherein:

the external interconnect structure comprises solder bumps;

the first terminal couples to the first external node through a first of the plurality of solder bumps; and

the second terminal couples to the second external node through a second of the plurality of solder bumps.