Stress relieving semiconductor layer

• US 9,330,906 B2
• Filed: 05/01/2014
• Issued: 05/03/2016
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Sun, Wenhong, Jain, Rakesh, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US14/266,900
• Publication Number:
  US 20140326950A1
• Time in Patent Office: 733 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer

Abstract

A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Claims

1. A structure comprising:

a substrate;

a nucleation layer located on the substrate, wherein the nucleation layer has a thickness of at least one nanometer and contains no large scale cavities, and wherein the cavity containing layer is located directly on the nucleation layer; and

a cavity containing layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

2. The structure of claim 1, wherein the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

3. The structure of claim 1, wherein the characteristic size is in a range of approximately ten nanometers to approximately four thousand nanometers.

4. The structure of claim 1, further comprising a semiconductor layer immediately adjacent to the cavity containing layer, wherein the semiconductor layer contains no large scale cavities.

5. The structure of claim 4, wherein the semiconductor layer is located on an opposing side of the cavity containing layer as a substrate.

6. The structure of claim 4, wherein the cavity containing layer and the semiconductor layer are part of a superlattice of semiconductor layers including a plurality of cavity containing layers interchanged with a plurality of semiconductor layers.

7. The structure of claim 1, further comprising a second cavity containing layer, wherein the second cavity containing layer has a thickness greater than two monolayers and a plurality of cavities, and wherein the plurality of cavities of the second cavity containing layer have a characteristic size of at least one nanometer and are separated from each other by at least five nanometers.

8. The structure of claim 7, further comprising a nucleation layer located between the cavity containing layer and the second cavity containing layer, wherein the nucleation layer has a thickness of at least one nanometer and contains no large scale cavities.

9. A device comprising:

a cavity containing layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer; and

a semiconductor layer immediately adjacent to the cavity containing layer, wherein the semiconductor layer contains no cavities, wherein the cavity containing layer and the semiconductor layer are formed of a uniform composition.

10. The device of claim 9, further comprising:

a substrate; and

a nucleation layer located on the substrate, wherein the nucleation layer has a thickness of at least one nanometer and contains no large scale cavities, and wherein the cavity containing layer is located directly on the nucleation layer.

11. The device of claim 9, wherein the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

12. The device of claim 9, wherein the cavity containing layer and the semiconductor layer are a part of a superlattice of semiconductor layers including a plurality of cavity containing layers interchanged with a plurality of semiconductor layers.

13. The device of claim 12, wherein at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers have thicknesses that vary by at least five percent within the superlattice.

14. The device of claim 13, wherein the at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers have increasing thicknesses from a first side of the superlattice to a second side of the superlattice.

15. The device of claim 13, wherein the device is configured to operate as one of:

a laser diode, a light emitting diode, a photodiode, a deep ultraviolet light emitting diode, a high mobility electron transistor, a field effect transistor, a p-n diode, or a Schottky diode.

16. A method comprising:

fabricating a semiconductor structure, wherein the fabricating includes;

growing a nucleation layer on a substrate, wherein the nucleation layer has a thickness of at least one nanometer and contains no large scale cavities; and

forming a cavity containing layer directly on the nucleation layer, wherein the cavity containing layer has a thickness greater than two monolayers and a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

17. The method of claim 16, wherein the cavity containing layer forming includes controlling a vertical size of the plurality of cavities by altering a lateral growth rate of island formations.

18. The method of claim 16, wherein the fabricating further includes growing a semiconductor layer on the cavity containing layer, wherein the semiconductor layer contains no large scale cavities.

19. The method of claim 16, further comprising fabricating a device using the structure.

20. The method of claim 16, wherein the cavity containing layer forming includes inducing the plurality of cavities using an auxiliary agent.