CMOS NFET and PFET comparable spacer width
First Claim
1. A method comprising:
- forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device), each having sidewall spacers on opposite sidewalls of a dummy gate, and source drain regions adjacent to the sidewall spacers;
conformally forming a first liner on the sidewall spacers of both the pFET device and the nFET device;
depositing a fill material directly above and in direct contact with the first liner, such that an upper surface of the fill material is substantially flush with an upper surface of a portion of the first liner above the dummy gates of both the pFET device and the nFET device;
removing a portion of the fill material and a portion of the first liner to expose only the pFET device, an etch rate of the first liner is substantially different from an etch rate of the sidewall spacers of the pFET device, such that the portion of the first liner is removed in its entirety selective to the sidewall spacers of the pFET device;
conformally forming a second liner above and in direct contact with the pFET device and along a vertical sidewall of a remaining portion of the fill material above the nFET device;
depositing a first inter level dielectric above the second liner;
removing the remaining portion of the fill material and a remaining portion of the first liner to expose the nFET device, the etch rate of the first liner is substantially different from an etch rate of the sidewall spacers of the nFET device, such that the remaining portion of the first liner is removed in its entirety selective to the sidewall spacers of the nFET device; and
conformally forming a third liner above and in direct contact with the nFET device and in direct contact with a vertical portion of the second liner.
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Accused Products
Abstract
A method including forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a dummy gate, conformally forming a first liner on the nFET device and depositing a fill material directly on the first liner of the nFET device, protecting the nFET device while growing an epitaxy in a source drain region of the pFET device, conformally forming a second liner above and in direct contact with the pFET device, including the epitaxy in the source drain regions of the pFET device, and along a vertical sidewall of a remaining portion of the fill material above the nFET device, depositing a first inter level dielectric above the second liner, and protecting the pFET device and the first inter level dielectric while growing a second epitaxy in a source drain region of the nFET device.
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Citations
15 Claims
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1. A method comprising:
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forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device), each having sidewall spacers on opposite sidewalls of a dummy gate, and source drain regions adjacent to the sidewall spacers; conformally forming a first liner on the sidewall spacers of both the pFET device and the nFET device; depositing a fill material directly above and in direct contact with the first liner, such that an upper surface of the fill material is substantially flush with an upper surface of a portion of the first liner above the dummy gates of both the pFET device and the nFET device; removing a portion of the fill material and a portion of the first liner to expose only the pFET device, an etch rate of the first liner is substantially different from an etch rate of the sidewall spacers of the pFET device, such that the portion of the first liner is removed in its entirety selective to the sidewall spacers of the pFET device; conformally forming a second liner above and in direct contact with the pFET device and along a vertical sidewall of a remaining portion of the fill material above the nFET device; depositing a first inter level dielectric above the second liner; removing the remaining portion of the fill material and a remaining portion of the first liner to expose the nFET device, the etch rate of the first liner is substantially different from an etch rate of the sidewall spacers of the nFET device, such that the remaining portion of the first liner is removed in its entirety selective to the sidewall spacers of the nFET device; and conformally forming a third liner above and in direct contact with the nFET device and in direct contact with a vertical portion of the second liner. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a dummy gate; conformally forming a first liner on the nFET device and depositing a fill material directly on the first liner of the nFET device; protecting the nFET device while growing an epitaxy in a source drain region of the pFET device; conformally forming a second liner above and in direct contact with the pFET device, including the epitaxy in the source drain regions of the pFET device, and along a vertical sidewall of a remaining portion of the fill material above the nFET device; depositing a first inter level dielectric above the second liner; and protecting the pFET device and the first inter level dielectric while growing a second epitaxy in a source drain region of the nFET device. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification