Integrated circuit with trimming

• US 9,331,086 B2
• Filed: 07/14/2009
• Issued: 05/03/2016
• Est. Priority Date: 07/23/2008
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Noort, Wibo D., Letavic, Theodore J., Zaato, Francis
• Primary Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US13/055,211
• Publication Number:
  US 20110186919A1
• Time in Patent Office: 2,485 Days
• Field of Search: 365/185.05, 365/149, 36518501-18528
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03M 1/802 using capacitors, e.g. neuron-mos transistors, charge coupled devices
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Claims

1. Integrated circuit, comprising:

at least one first group each having at least one analog circuit;

at least one second group each having at least one electronically settable semi-permanent switching circuit coupled to the at least one analog circuit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell;

wherein each many-times-programmable cell comprises at least one MOS transistor connected in series with one of the analog circuits and having a source and drain in parallel with a source and drain of at least another MOS transistor in another one of the many-times-programmable cells, and having a floating gate with a tunnel oxide and a first capacitor coupled to the floating gate; and

wherein the capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor;

wherein the at least one analog circuit comprises at least one of a capacitor, an inductor, and a time delay unit, and

wherein the at least on electronically settable semi-permanent switching circuit includes a plurality of switching circuits that are grouped in bits, where the nth bit contains 2n many-times-programmable cells, where n is a positive integer.

2. Integrated circuit according to claim 1, wherein the first capacitor comprises a tunnel oxide as dielectric material, wherein a tunneling current is induced when a programming voltage across the many-times-programmable cell is sufficiently high and wherein a charge which has tunneled remains trapped when the programming voltage is reduced,

wherein the first capacitor is configured and arranged to set a potential of the floating gate to provide non-volatile charge storage in the floating gate, and wherein the at least one electronically settable semi-permanent switching circuit is configured and arranged to retain a position by storing electric charge on the floating gates that is independent of a voltage supply being present.

3. Integrated circuit according to claim 1, wherein the integrated circuit is a CMOS implementation and the first capacitor is implemented as a transistor with its gate coupled to the floating gate.

4. Integrated circuit according to claim 1, wherein the integrated circuit is a BiCMOS implementation and the first capacitor is implemented as a capacitor coupled between the floating gate and a base poly layer.

5. Integrated circuit according to claim 1, wherein a thickness of the tunnel oxide is from 50-100 Å

, and wherein the at least one MOS transistor has a programming voltage of about 12V.

6. Integrated circuit according to claim 1, further including at least one of a phased-array antenna, an oscillator, a filter, and a matching device and wherein the at least on electronically settable semi-permanent switching circuit is configured and arranged retain a position by storing the electric charge on the respective floating gates for a duration of at least ten years and wherein the trimming is reversible for re-calibration.

7. Integrated circuit according to claim 1, wherein each of the at least one analog circuits is a second capacitor connected directly to ground, the at least one MOS transistor being connected directly to the second capacitor and configured and arranged to trim the second capacitor based upon data stored in the non-volatile cell.

8. The integrated circuit of claim 1, wherein

the first capacitor is configured and arranged to provide a voltage division between the first capacitor and a second capacitor including the floating gate and a channel of the MOS transistor as separated by the tunnel oxide, according to a capacitance ratio of the first and second capacitors and

the first and second capacitors are configured and arranged to provide a voltage drop and to apply the voltage drop to the tunnel oxide.

9. The integrated circuit of claim 1, wherein the electrically settable semi-permanent switching circuit is configured and arranged to electrically set the switch by:

measuring a threshold voltage of the floating gate; and

programming the switching circuit by applying a programming voltage to the floating gate.

10. An apparatus comprising:

an analog circuit; and

a plurality of electrically settable semi-permanent switching circuits communicatively coupled to the analog unit and configured and arranged to trim the analog circuit in an electrical domain each switching circuit including a many-times-programmable non-volatile memory circuit having

a first capacitor, and

at least one MOS transistor including a source and drain in parallel with a source and drain of the at least one MOS transistor of another one of the electrically settable semi-permanent switching circuits, a channel, a floating gate and a tunnel oxide, the floating gate being coupled to the first capacitor, the first capacitor being configured and arranged with a capacitance substantially larger than a gate-channel capacitance of the MOS transistor,

wherein the first capacitor is configured and arranged to set the potential of the floating gate to provide non-volatile charge storage in the floating gate and wherein the plurality of electrically settable semi-permanent switching circuits are configured and arranged to retain a position by storing electric charge on the floating gates that is independent of a voltage supply;

wherein the electrically settable semi-permanent switching circuit is configured and arranged to electrically set the switch by;

measuring a threshold voltage of the floating gate;

programming the switching circuit by applying a programming voltage to the floating gate; and

wherein the plurality of electronically settable semi-permanent switching circuits are grouped in bits, where the nth bit contains 2n many-times-programmable cells, where n is a positive integer.

11. The apparatus of claim 10 wherein the electrically settable semi-permanent switching circuit is further configured and arranged to reversibly trim the analog circuit in an electrical domain, utilizing at least one of the many-times-programmable non-volatile memory circuits.

12. The apparatus of claim 10, wherein the electrically settable semi-permanent switching circuit is configured and arranged to trim the analog circuit by selectively coupling the analog circuit to at least one other analog circuit via at least one of the switching circuits, based upon a charge on the floating gate of the at least one of the switching circuits.

13. The apparatus of claim 10, wherein each MOS transistor is connected to another analog circuit and the apparatus is configured and arranged to trim the analog circuit by connecting the analog circuit to at least one of the other analog circuits by controlling the floating gate of at least one of the MOS transistors.

14. The apparatus of claim 13, wherein each of the other analog circuits is a capacitor and the apparatus is configured and arranged to trim a capacitance of the analog circuit by controlling the plurality of switching circuits to connect the analog circuit to at least one of the capacitors.

15. The apparatus of claim 13, wherein each of the other analog circuits is an inductor and the apparatus is configured and arranged to trim an inductance of the analog circuit by controlling the plurality of switching circuits to connect the analog circuit to at least one of the inductors in series.

16. The apparatus of claim 10, wherein

the first capacitor is configured and arranged provide a voltage division between the first capacitor and a second capacitor that includes the floating gate and a channel of the at least one MOS transistor as separated by the tunnel oxide, according to a capacitance ratio of the first and second capacitors, and

the first and second capacitors are configured and arranged to provide a voltage drop and to apply the voltage drop to the tunnel oxide.