Integrated circuit with trimming
First Claim
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1. Integrated circuit, comprising:
- at least one first group each having at least one analog circuit;
at least one second group each having at least one electronically settable semi-permanent switching circuit coupled to the at least one analog circuit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell;
wherein each many-times-programmable cell comprises at least one MOS transistor connected in series with one of the analog circuits and having a source and drain in parallel with a source and drain of at least another MOS transistor in another one of the many-times-programmable cells, and having a floating gate with a tunnel oxide and a first capacitor coupled to the floating gate; and
wherein the capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor;
wherein the at least one analog circuit comprises at least one of a capacitor, an inductor, and a time delay unit, andwherein the at least on electronically settable semi-permanent switching circuit includes a plurality of switching circuits that are grouped in bits, where the nth bit contains 2n many-times-programmable cells, where n is a positive integer.
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Abstract
An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.
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Citations
16 Claims
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1. Integrated circuit, comprising:
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at least one first group each having at least one analog circuit; at least one second group each having at least one electronically settable semi-permanent switching circuit coupled to the at least one analog circuit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell; wherein each many-times-programmable cell comprises at least one MOS transistor connected in series with one of the analog circuits and having a source and drain in parallel with a source and drain of at least another MOS transistor in another one of the many-times-programmable cells, and having a floating gate with a tunnel oxide and a first capacitor coupled to the floating gate; and wherein the capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor; wherein the at least one analog circuit comprises at least one of a capacitor, an inductor, and a time delay unit, and wherein the at least on electronically settable semi-permanent switching circuit includes a plurality of switching circuits that are grouped in bits, where the nth bit contains 2n many-times-programmable cells, where n is a positive integer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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an analog circuit; and a plurality of electrically settable semi-permanent switching circuits communicatively coupled to the analog unit and configured and arranged to trim the analog circuit in an electrical domain each switching circuit including a many-times-programmable non-volatile memory circuit having a first capacitor, and at least one MOS transistor including a source and drain in parallel with a source and drain of the at least one MOS transistor of another one of the electrically settable semi-permanent switching circuits, a channel, a floating gate and a tunnel oxide, the floating gate being coupled to the first capacitor, the first capacitor being configured and arranged with a capacitance substantially larger than a gate-channel capacitance of the MOS transistor, wherein the first capacitor is configured and arranged to set the potential of the floating gate to provide non-volatile charge storage in the floating gate and wherein the plurality of electrically settable semi-permanent switching circuits are configured and arranged to retain a position by storing electric charge on the floating gates that is independent of a voltage supply; wherein the electrically settable semi-permanent switching circuit is configured and arranged to electrically set the switch by; measuring a threshold voltage of the floating gate; programming the switching circuit by applying a programming voltage to the floating gate; and wherein the plurality of electronically settable semi-permanent switching circuits are grouped in bits, where the nth bit contains 2n many-times-programmable cells, where n is a positive integer. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification