Back side illuminated single photon avalanche diode imaging sensor with high short wavelength detection efficiency

• US 9,331,116 B2
• Filed: 01/15/2014
• Issued: 05/03/2016
• Est. Priority Date: 01/15/2014
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Webster, Eric A. G.
• Primary Examiner(s): Chen, Yu
• Assistant Examiner(s): Rahim, Nilufa
• Application Number:
  US14/156,053
• Publication Number:
  US 20150200314A1
• Time in Patent Office: 839 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures

Abstract

A single photon avalanche diode (SPAD) includes an n doped epitaxial layer disposed in a first semiconductor layer. A p doped epitaxial layer is above the n doped epitaxial layer on a back side of the first semiconductor layer. A multiplication junction is defined at an interface between the n doped epitaxial layer and the p doped epitaxial layer. A multiplication junction is reversed biased above a breakdown voltage such that a photon received through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction. A p− doped guard ring region is implanted in the n doped epitaxial layer surrounding the multiplication junction.

Claims

1. A single photon avalanche diode (SPAD), comprising:

an n doped epitaxial layer disposed in a first semiconductor layer;

a p doped epitaxial layer formed over the n doped epitaxial layer on a back side of the first semiconductor layer, wherein the p doped epitaxial layer covers the entire back side of the first semiconductor layer;

a multiplication junction defined at an interface between the n doped epitaxial layer and the p doped epitaxial layer, wherein a multiplication junction is reversed biased above a breakdown voltage such that a photon received through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction; and

a p−

doped guard ring region implanted in the n doped epitaxial layer surrounding the multiplication junction, wherein the p doped epitaxial layer covers the entire p−

doped guard ring from the back side of the first semiconductor layer.

2. The SPAD of claim 1 further comprising an n+ doped contact region disposed in the n doped epitaxial layer, wherein the n+ doped contact region is coupled to provide contact to the n doped epitaxial layer from a front side of the first semiconductor layer.

3. The SPAD of claim 1 further comprising a p+ doped contact region implanted within the p−

doped guard ring region, wherein the p+ doped contact region is coupled to provide contact to the p doped epitaxial layer from a front side of the first semiconductor layer.

4. The SPAD of claim 3 wherein the p+ doped contact region has a higher doping concentration than the p−

doped guard ring region.

5. The SPAD of claim 1 wherein the p doped epitaxial layer has a graded doping profile.

6. An imaging sensor system, comprising:

a first semiconductor layer of a first wafer;

a single photon avalanche diode (SPAD) imaging array including a plurality of pixels formed in the first semiconductor layer, wherein each pixel includes a SPAD including;

an n doped epitaxial layer disposed in the first semiconductor layer;

a p doped epitaxial layer formed over the n doped epitaxial layer on a back side of the first semiconductor layer, wherein the p doped epitaxial layer covers the entire back side of the first semiconductor layer;

a multiplication junction defined at an interface between the n doped epitaxial layer and the p doped epitaxial layer, wherein a multiplication junction is reversed biased above a breakdown voltage such that a photon received through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction;

a p−

doped guard ring region implanted in the n doped epitaxial layer surrounding the multiplication junction, wherein the p doped epitaxial layer covers the entire p−

doped guard ring from the back side of the first semiconductor layer;

a second semiconductor layer of a second wafer bonded to the first wafer;

a plurality of digital counters formed in the second semiconductor layer and electrically coupled to the SPAD imaging array, wherein each one of the plurality of digital counters is coupled to count output pulses generated by a respective one of the plurality of pixels.

7. The imaging sensor system of claim 6 wherein each SPAD further includes an n+ doped contact region disposed in the n doped epitaxial layer, wherein the n+ doped contact region is coupled to provide contact to the n doped epitaxial layer from a front side of the first semiconductor layer.

8. The imaging sensor system of claim 6 wherein each SPAD further includes a p+ doped contact region implanted within the p−

doped guard ring region, wherein the p+ doped contact region is coupled to provide contact to the p doped epitaxial layer from a front side of the first semiconductor layer.

9. The imaging sensor system of claim 8 wherein the p+ doped contact region has a higher doping concentration than the p−

doped guard ring region.

10. The imaging sensor system of claim 6 wherein the p doped epitaxial layer has a graded doping profile.

11. The imaging sensor system of claim 6 wherein each of the plurality of digital counters formed in the second semiconductor layer comprises a complementary metal oxide semiconductor (CMOS) circuit disposed in the second semiconductor layer of the second wafer.

12. The imaging sensor system of claim 6 wherein the plurality of pixels include an N number of pixels, wherein the plurality of digital counters includes at least N number of digital counters, and wherein each of the N number of digital counters is coupled to a respective one of the plurality of pixels.

13. The imaging sensor system of claim 6 further comprising:

a first interconnect layer disposed on the front side of the first semiconductor layer; and

a second interconnect layer disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first interconnect layer and the second interconnect layer.

14. The imaging sensor system of claim 13 wherein the first interconnect layer includes a first oxide, the second interconnect layer includes a second oxide, and wherein the bonding interface includes an interface between the first oxide and the second oxide.

15. The imaging sensor system of claim 14 wherein the first interconnect layer comprises a plurality of vias, wherein each one of the plurality of vias is coupled to a respective pixel of the SPAD imaging array to transfer the output pulses to the second interconnect layer at the bonding interface.

16. The imaging sensor system of claim 6, wherein each pixel comprises a quenching element coupled to a respective SPAD to quench avalanching of the respective SPAD by lowering a bias voltage.

17. The imaging sensor system of claim 6 further comprising control circuitry formed in the second semiconductor layer and coupled to the SPAD imaging array to control operation of the SPAD imaging array.

18. The imaging sensor system of claim 17 further comprising function logic formed in the second semiconductor layer and coupled to the plurality of digital counters to store data read out from the SPAD imaging array.