Silicon nanowire formation in replacement metal gate process

• US 9,331,146 B2
• Filed: 06/11/2014
• Issued: 05/03/2016
• Est. Priority Date: 06/11/2014
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Chia-Yu, Liu, Zuoguang, Yamashita, Tenko
• Primary Examiner(s): Patel, Reema
• Assistant Examiner(s): GHEYAS, SYED I
• Application Number:
  US14/301,587
• Publication Number:
  US 20150364543A1
• Time in Patent Office: 692 Days
• Field of Search: 438/253
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/31056 the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a fin structure in a substrate;

forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, wherein the protective layer is directly on and is the same on both sidewalls of the fin structure; and

defining a nanowire structure from the fin structure by performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer.

2. The method of claim 1, further comprising:

forming a sacrificial planarizing layer over the lower portion of the fin structure, such that the sacrificial planarizing layer abuts both of the sidewalls of the fin structure, wherein the material of the fin structure is different from the sacrificial planarizing layer abutting the sidewalls;

forming the protective layer over the sacrificial planarizing layer and the upper portions of the fin structure;

removing horizontal portions of the protective layer;

removing the sacrificial planarizing layer so as to expose the lower portion of the fin structure; and

performing the undercut etch on the lower portion of the fin structure having been exposed.

3. The method of claim 2, wherein the sacrificial planarizing layer is made of organic oxide and is formed over the device by spin coating followed by recessing.

4. The method of claim 1, wherein the protective layer comprises titanium nitride.

5. A method for fabricating a nanowire comprising:

depositing a protective layer on a fin structure, wherein the protective layer is directly on and is the same on both sidewalls of the fin structure;

etching at least a portion of the protective layer proximate to an optical planarization layer of the structure;

removing the optical planarization layer from the structure; and

providing an undercut etch to remove at least a portion of one or more fins of the structure.

6. The method of claim 5, wherein the etching of the at least the portion of the protective layer proximate to the optical planarization layer comprises reactive ion etching (RIE).

7. The method of claim 5, further comprising:

removing the remainder of the protective layer subsequent to the undercut etch.

8. The method of claim 5, further comprising:

removing one or more hard masks (HMs) associated with the one or more fins of the structure.

9. The method of claim 5, further comprising:

applying a high-k deposit, a work function metal (WFM), and a tungsten deposit to the structure.

10. The method of claim 5, further comprising:

applying a chemical mechanical planarization (CMP) process to the structure.

11. The method of claim 5, wherein the protective layer comprises titanium nitride.

12. The method of claim 5, wherein the optical planarization layer is made of organic oxide.