Single power supply level shifter

• US 9,331,516 B2
• Filed: 05/18/2014
• Issued: 05/03/2016
• Est. Priority Date: 05/18/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Goyal, Gaurav
• Primary Examiner(s): Crawford, Jason M
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US14/280,655
• Publication Number:
  US 20150333556A1
• Time in Patent Office: 716 Days
• US Class Current: 1/1
• CPC Class Codes: H02J 1/082 Plural DC voltage, e.g. DC supply voltage with at least two different DC voltage levels
• CPC Class Codes: H02J 7/0042 characterised by the mechanical construction
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low.

Claims

1. A single power supply level shifter for a semiconductor device having first and second power supply voltage domains, the level shifter comprising:

a first inverter inverting an input signal from the first voltage domain and providing a first inverted signal in the second voltage domain;

a second inverter inverting the first inverted signal and providing an output signal in the second voltage domain;

a capacitor element;

a charging control circuit charging the capacitor element towards the second voltage when the input signal is high, and conducting a discharge current from the capacitor element during a transition of the input signal from high to low, wherein the discharge current accelerates a corresponding transition of the first inverted signal from low to high;

a current reduction module having a current conduction path of a current reduction transistor connected in series with a current conduction path of the first inverter; and

a third inverter providing a third inverted signal in the second voltage domain to a control electrode of the current reduction transistor to reduce the current in the current reduction transistor and the first inverter when the first inverted signal is low, wherein the charging control circuit charges the capacitor from the third inverted signal when the input signal is high.

2. The level shifter of claim 1, wherein the charging control circuit conducts the discharge current from the capacitor element during a transition of the input signal and the third inverted signal from high to low.

3. The level shifter of claim 2, wherein the charging control circuit includes:

a first control transistor of a first type and having a control electrode connected to the output of the first inverter and a current conduction path connected between the output of the third inverter and the capacitor element for charging the capacitor element;

a second control transistor of the first type and having a control electrode connected to the output of the third inverter and a current conduction path connected between the output of the first inverter and the capacitor element for conducting the discharge current; and

a third control transistor of the opposite type to the first type and having a control electrode connected to the output of the third inverter and a current conduction path connected between the input of the first inverter and the control electrode of the second control transistor.

4. The level shifter of claim 1, wherein the inverters are complementary metal-oxide semiconductor (CMOS) inverters.

5. The level shifter of claim 4, wherein each of the inverters has a p-channel transistor and an n-channel transistor, the p-channel transistor having a current conduction path connected between the n-channel transistor and a power voltage supply, and the n-channel transistor having a current conduction path connected between the p-channel transistor and ground.

6. A level shifter for converting an input signal from a first domain at a first power supply voltage to an output signal for a second domain at a second power supply voltage, the level shifter comprising:

a first inverter having a first output connected in series between first and second power supply terminals in the second domain to invert the input signal and provide a first inverted signal;

a second inverter having a second output connected in series between the first and second power supply terminals in the second domain to invert the first inverted signal and provide the output signal;

a current reduction transistor having a control terminal, and a current conduction path connected in series between the first output and the first power supply terminal;

a third inverter having a third output connected in series between the first and second power supply terminals in the second domain to invert the first inverted signal and provide a third inverted signal on the control terminal to reduce the current in the current reduction transistor and the first inverter when the first inverted signal is low;

a capacitor; and

a charging control circuit having a first control transistor having a control terminal connected to the first output and a current conduction path connected to the third output for charging the capacitor towards the second voltage when the input signal is high, and a second control transistor having a control terminal connected to the third output and a current conduction path connected to the first output for conducting a discharge current from the capacitor during a transition of the input signal and the third inverted signal from high to low, wherein the discharge current accelerates a corresponding transition of the first inverted signal from low to high.

7. The level shifter of claim 6, wherein the second control transistor conducts the discharge current from the capacitor when the input signal and the third inverted signal are low.

8. The level shifter of claim 7, wherein the first and second control transistors are of a first type, and the charging control circuit includes a third control transistor of the opposite type to the first type and having a control electrode connected to the output of the third inverter and a current conduction path connected between the input of the first inverter and the control electrode of the second control transistor to accelerate the second control transistor conducting the discharge current from the capacitor element during the transition of the input signal from high to low.

9. The level shifter of claim 6, wherein the inverters are complementary metal-oxide semiconductor (CMOS) inverters.

10. The level shifter of claim 9, wherein each of the inverters has a p-channel transistor and an n-channel transistor, the p-channel transistor having a current conduction path connected between the n-channel transistor and a power voltage supply, and the n-channel transistor having a current conduction path connected between the p-channel transistor and ground.