Doherty power amplifier apparatus

• US 9,331,638 B2
• Filed: 10/26/2011
• Issued: 05/03/2016
• Est. Priority Date: 04/29/2011
• Status: Active Grant

• Current Assignee: ZTE Corporation
• Original Assignee: ZTE Corporation
• Inventors: Chen, Huazhang, Liu, Jianli, An, Jinyuan, Cui, Xiaojun
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US13/514,696
• Publication Number:
  US 20150349719A1
• Time in Patent Office: 1,651 Days
• Field of Search: 330/124.R, 330/295, 330/310
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/405 the output amplifying stage of an amplifier comprising more than three power stages
• CPC Class Codes: H03F 2200/447 the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only

Abstract

Disclosed is a Doherty power amplifier apparatus, including: a drive amplifier circuit, a power splitter circuit and a power combiner circuit, wherein the power splittercircuit is connected to the drive amplifier circuit, the apparatus further comprising: a carrier amplifier circuit and a peak amplifier circuit connected in parallel between the power splitter circuit and the power combiner circuit, wherein the carrier amplifier circuit comprises one or more parallel carrier amplification branches, wherein each carrier amplification branch comprises a multi-stage carrier amplifier apparatus, the multi-stage carrier amplifier apparatus is used for achieving multi-stage carrier amplification; and the peak amplifier circuit comprises one or more parallel peak amplification branches, wherein each peak amplification branch comprises a multi-stage peak amplifier apparatus, the multi-stage peak amplifier apparatus is used for achieving multi-stage peak amplification.

Claims

1. A Doherty power amplifier apparatus, comprising:

a drive amplifier circuit, a power splitter, a carrier amplifier circuit, a peak amplifier circuit and a power combiner, one end of the power splitter connected to the drive amplifier circuit, the carrier amplifier circuit and the peak amplifier circuit connected in parallel between the other end of the power splitter and the power combiner, wherein,

the carrier amplifier circuit comprises one or more parallel carrier amplification branches, each carrier amplification branch comprises a multi-stage carrier amplifier apparatus, and the multi-stage carrier amplifier apparatus is used for achieving multi-stage carrier amplification; and

the peak amplifier circuit comprises one or more parallel peak amplification branches, each peak amplification branch comprises a multi-stage peak amplifier apparatus, and the multi-stage peak amplifier apparatus is used for achieving multi-stage peak amplification;

wherein, the multi-stage peak amplifier apparatus comprises N1 serial peak amplifiers in which M1 serial peak amplifiers are integrated into a first integrated circuit, where M1 and N1 are integers, N1>

2 and 1 <

M1<

N1, and

wherein, the multi-stage carrier amplifier apparatus comprises N2 serial carrier amplifiers in which M2 serial carrier amplifiers are integrated into a second integrated circuit, where M2 and N2 are integers, N2>

2 and 1<

M2<

N2;

a power distribution of the peak amplification branch(es) and the carrier amplification branch(es) is regulated within a large range by changing a static offset voltage of the first integrated circuit and/or the second integrated circuit to solve a problem of reduced efficiency and linearity caused by the discretion of the input standing waves of the power amplifier during batch manufacture of the Doherty power amplifier.

2. The apparatus as claimed in claim 1, wherein the multi-stage peak amplifier apparatus further comprises a power regulation apparatus connected to at least one of the (N1-M1) peak amplifiers, and the power regulation apparatus is used for regulating a power of the corresponding peak amplifier.

3. The apparatus as claimed in claim 1, wherein the multi-stage carrier amplifier apparatus further comprises a power regulation apparatus connected to at least one of the (N2-M2) carrier amplifiers, and the power regulation apparatus is used for regulating a power of the corresponding carrier amplifier.

4. The apparatus as claimed in claim 1, wherein first M1 serial peak amplifiers, which are close to the power splitter, of the multi-stage peak amplifier apparatus are implemented by the first integrated circuit.

5. The apparatus as claimed in claim 1, wherein first M2 serial carrier amplifiers, which are close to the power splitter, of the multi-stage carrier amplifier apparatus are implemented by the second integrated circuit.

6. The apparatus as claimed in claim 1, wherein the last one peak amplifier, which is close to the power combiner, of the multi-stage peak amplifier apparatus is implemented by one peak amplifier.

7. The apparatus as claimed in claim 4, wherein the last one peak amplifier, which is close to the power combiner, of the multi-stage peak amplifier apparatus is implemented by one peak amplifier.

8. The apparatus as claimed in claim 1, wherein the last one carrier amplifier, which is close to the power combiner, of the multi-stage carrier amplifier apparatus is implemented by one carrier amplifier.

9. The apparatus as claimed in claim 5, wherein the last one carrier amplifier, which is close to the power combiner, of the multi-stage carrier amplifier apparatus is implemented by one carrier amplifier.

10. The apparatus as claimed in claim 1, wherein the first integrated circuit and the second integrated circuit are implemented on one integrated circuit chip.