Level shifter circuit

• US 9,331,698 B2
• Filed: 01/02/2014
• Issued: 05/03/2016
• Est. Priority Date: 01/02/2014
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Jain, Deependra K., Thakur, Krishna
• Primary Examiner(s): Chen, Sibin
• Assistant Examiner(s): RETEBO, METASEBIA T
• Application Number:
  US14/146,721
• Publication Number:
  US 20150188543A1
• Time in Patent Office: 852 Days
• Field of Search: 327156-159
• US Class Current: 1/1
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.

Claims

1. A level-shifter circuit for generating an output voltage based on an input voltage, comprising:

an input stage for generating an inverted input voltage, wherein the input stage includes;

a first transistor having a gate terminal for receiving a first supply voltage and a source terminal connected to ground;

a second transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the first transistor and a source terminal for receiving a second supply voltage;

a third transistor having a gate terminal connected to the gate terminal of the second transistor and a source terminal for receiving the second supply voltage;

a fourth transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the third transistor and a source terminal connected to ground; and

a fifth transistor having a gate terminal for receiving the input voltage, a drain terminal connected to the gate terminal of the fourth transistor, and a source terminal connected to ground, wherein the inverted input voltage is generated at the drain terminal thereof; and

a driver stage, connected to the input stage, for level shifting the input voltage that is at a level of the first supply voltage to the output voltage, wherein the driver stage includes;

a sixth transistor having a gate terminal connected to the gate and drain terminals of the fourth and fifth transistors, respectively, and a source terminal connected to ground;

a seventh transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the sixth transistor and a source terminal for receiving the second supply voltage;

an eighth transistor having a gate terminal connected to the gate terminal of the seventh transistor and a source terminal for receiving the second supply voltage; and

a ninth transistor having a gate terminal for receiving the input voltage, a source terminal connected to ground, and a drain terminal connected to a drain terminal of the eighth transistor for outputting the output voltage, wherein the output voltage is at a level of the second supply voltage.

2. The level-shifter circuit of claim 1, wherein the first, fourth, fifth, sixth, and ninth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.

3. The level-shifter circuit of claim 1, wherein the second, third, seventh, and eighth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.

4. The level-shifter circuit of claim 1, further comprising an inverter connected to the drain terminal of the ninth transistor for buffering the output voltage.

5. A voltage-controlled oscillator (VCO), comprising:

a voltage-to-current converter, for receiving an input voltage and generating an output current;

a current-controlled ring oscillator, connected to the voltage-to-current converter, wherein the current-controlled ring oscillator includes a plurality of inverters that receive the output current and generate corresponding plurality of oscillating signals by using a top-node voltage of the current-controlled ring oscillator, wherein the plurality of oscillating signals have a predetermined phase difference therebetween and each oscillating signal has a voltage level that is equal to the top-node voltage; and

a level-shifter circuit, connected to the current-controlled ring oscillator, for receiving a first oscillating signal of the plurality of oscillating signals and level shifting a voltage level of the first oscillating signal from the top-node voltage to an output voltage, wherein the level-shifter circuit comprises;

an input stage for generating an inverted first oscillating signal, wherein the input stage includes;

a first transistor having a gate terminal for receiving the top-node voltage and a source terminal connected to ground;

a second transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the first transistor and a source terminal for receiving a supply voltage;

a third transistor having a gate terminal connected to the gate terminal of the second transistor and a source terminal for receiving the supply voltage;

a fourth transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the third transistor and a source terminal connected to ground; and

a fifth transistor having a gate terminal for receiving the first oscillating signal, a drain terminal connected to the gate terminal of the fourth transistor, and a source terminal connected to ground, wherein the inverted first oscillating signal is generated at the drain terminal thereof; and

a driver stage, connected to the input stage, for generating the output voltage, wherein the driver stage includes;

a sixth transistor having a gate terminal connected to the gate and drain terminals of the fourth and fifth transistors, respectively, and a source terminal connected to ground;

a seventh transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the sixth transistor and a source terminal for receiving the supply voltage;

an eighth transistor having a gate terminal connected to the gate terminal of the seventh transistor and a source terminal for receiving the supply voltage; and

a ninth transistor having a gate terminal for receiving the first oscillating signal, a source terminal connected to ground, and a drain terminal connected to a drain terminal of the eighth transistor for outputting the output voltage, wherein the output voltage is at a level of the supply voltage.

6. The VCO of claim 5, wherein the first, fourth, fifth, sixth, and ninth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.

7. The VCO of claim 5, wherein the second, third, seventh, and eighth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.

8. The VCO of claim 5, further comprising an inverter, connected to the drain terminal of the ninth transistor, for buffering the output voltage.

9. The VCO of claim 5, wherein the predetermined phase difference is 120 degrees.

10. A phase-locked loop (PLL), comprising:

a voltage-controlled oscillator (VCO) for generating a plurality of oscillating signals, wherein the VCO comprises;

a voltage-to-current converter, for receiving an input voltage and generating an output current;

a current-controlled ring oscillator, connected to the voltage-to-current converter, wherein the current-controlled ring oscillator includes a plurality of inverters that receive the output current and generate the corresponding plurality of oscillating signals by using a top-node voltage of the current-controlled ring oscillator, wherein the plurality of oscillating signals have a predetermined phase difference therebetween and each oscillating signal has a voltage level equal to the top-node voltage; and

a level-shifter circuit, connected to the current-controlled ring oscillator, for receiving a first oscillating signal of the plurality of oscillating signals and level shifting a voltage level of the first oscillating signal from the top-node voltage to an output voltage, wherein the level-shifter circuit comprises;

an input stage for generating an inverted first oscillating signal, wherein the input stage includes;

a first transistor having a gate terminal for receiving the top-node voltage and a source terminal connected to ground;

a second transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the first transistor and a source terminal for receiving a supply voltage;

a third transistor having a gate terminal connected to the gate terminal of the second transistor and a source terminal for receiving the supply voltage;

a fourth transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the third transistor and a source terminal connected to ground; and

a fifth transistor having a gate terminal for receiving the first oscillating signal, a drain terminal connected to the gate terminal of the fourth transistor, and a source terminal connected to ground, wherein the inverted first oscillating signal is generated at the drain terminal thereof; and

a driver stage, connected to the input stage, for generating the output voltage, wherein the driver stage includes;

a sixth transistor having a gate terminal connected to the gate and drain terminals of the fourth and fifth transistors, respectively, and a source terminal connected to ground;

a seventh transistor having a drain terminal connected to a gate terminal thereof and a drain terminal of the sixth transistor and a source terminal for receiving the supply voltage;

an eighth transistor having a gate terminal connected to the gate terminal of the seventh transistor and a source terminal for receiving the supply voltage; and

a ninth transistor having a gate terminal for receiving the first oscillating signal, a source terminal connected to ground, and a drain terminal connected to a drain terminal of the eighth transistor for outputting the output voltage, wherein the output voltage is at a level of the supply voltage.

11. The PLL of claim 10, wherein the first, fourth, fifth, sixth, and ninth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.

12. The PLL of claim 10, wherein the second, third, seventh, and eighth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.

13. The PLL of claim 10, further comprising an inverter, connected to the drain terminal of the ninth transistor, for buffering the output voltage.

14. The PLL of claim 10, wherein the predetermined phase difference is 120 degrees.