Level shifters, memory systems, and level shifting methods

• US 9,331,699 B2
• Filed: 01/08/2014
• Issued: 05/03/2016
• Est. Priority Date: 01/08/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Luthra, Yogesh
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/150,228
• Publication Number:
  US 20150194961A1
• Time in Patent Office: 846 Days
• Field of Search: 365/148, 365/189.09, 365/189.11, 365/203
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS

Abstract

Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.

Claims

1. A level shifter comprising:

an input configured to receive an input signal in a first voltage domain;

an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain;

a plurality of pull-down devices, and wherein one of the pull-down devices is directly coupled with the input and the output;

a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal;

a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices; and

a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.

2. The level shifter of claim 1 wherein the dynamic devices only conduct current as a result of the transitions in the input signal.

3. The level shifter of claim 1 wherein the dynamic devices conduct the charging current during the transitions in the output signal.

4. The level shifter of claim 1 wherein the dynamic devices are coupled in parallel with respective ones of the current limiting devices.

5. The level shifter of claim 1 further comprising an inverter intermediate the one of the pull-down devices and the output.

6. The level shifter of claim 1 wherein the one of the pull-down devices, one of the cross-coupled devices, one of the current-limiting devices and one of the dynamic devices conduct current in one of a plurality of circuit branches.

7. The level shifter of claim 1 further comprising an output node intermediate the output and the one pull-down device, and a gate of one of the cross-coupled devices is coupled with the output node and a gate of another cross-coupled device is directly coupled with another of the pull-down devices.

8. The level shifter of claim 1 further comprising bias circuitry configured to apply mirrored bias signals to gates of the plurality of current limiting devices to cause the current limiting devices to conduct the current during the transitions in the output signal.

9. A level shifter comprising:

an input configured to receive an input signal in a first voltage domain;

supply circuitry configured to provide electrical energy from a source to an output node;

dynamic circuitry configured to provide electrical energy from the source to the output node during transitions in an output signal; and

an output coupled with the output node and configured to output the output signal from the level shifter in a second voltage domain; and

bias circuitry configured to apply bias signals to the supply circuitry to cause the supply circuitry to provide the electrical energy from the source to the output node during the transitions in the output signal.

10. The level shifter of claim 9 wherein the transitions in the output signal result from transitions in the input signal.

11. The level shifter of claim 9 wherein the dynamic circuitry only conducts current as a result of transitions in the input signal.

12. The level shifter of claim 9 wherein the supply circuitry comprises current limiting circuitry configured to limit an amount of the electrical energy provided from the source via the current limiting circuitry to the output node.

13. The level shifter of claim 12 wherein the dynamic circuitry is coupled in parallel with the current limiting circuitry.

14. The level shifter of claim 9 further comprising an inverter intermediate the output node and the output.

15. The level shifter of claim 9 wherein the supply circuitry and the dynamic circuitry individually comprise a plurality of devices which are arranged in a plurality of circuit branches.

16. The level shifter of claim 15 wherein the bias circuitry is configured to apply the bias signals comprising mirrored bias signals to the circuit branches.

17. The level shifter of claim 15 further comprising cross-coupled circuitry coupled intermediate the circuit branches.

18. The level shifter of claim 12 wherein the dynamic circuitry is controlled to provide the electrical energy to the output node to provide an increased rate of charge of the output node following a transition in the input signal compared with a rate of charge resulting from provision of current only using the current limiting circuitry.

19. The level shifter of claim 9 wherein the provision of the electrical energy to the output node via the supply circuitry and the dynamic circuitry causes the transitions in the output signal which correspond to transitions in the input signal.

20. A memory system comprising:

level shifter circuitry comprising an input configured to receive an input signal in a first voltage domain, pull-up circuitry configured to selectively pull an output node to a high voltage level, pull-down circuitry configured to selectively pull the output node to a low voltage level, charging circuitry configured to provide a plurality of current signals in parallel to the output node to charge the output node following a transition in the input signal, and an output coupled with the output node and configured to output an output signal in a second voltage domain different than the first voltage domain from the level shifter circuitry; and

memory circuitry coupled with the level shifter circuitry and configured to use the output signal to store digital data in a plurality of memory cells.

21. The system of claim 20 wherein the provision of the plurality of parallel current signals to the output node causes a transition in the output signal which corresponds to the transition in the input signal.

22. The system of claim 20 wherein the charging circuitry includes dynamic circuitry and current limiting circuitry coupled in parallel and configured to provide the parallel current signals to the output node, wherein the dynamic circuitry is configured to only conduct current as a result of the transition and other transitions in the input signal.

23. The system of claim 20 wherein the memory cells are individually configured to have different electrical resistances in different memory states to store the digital data.

24. A level shifting method comprising:

receiving an input signal in a first voltage domain;

generating an output signal in a second voltage domain different than the first voltage domain and comprising a plurality of transitions corresponding to transitions in the input signal, the generating comprising generating using electrical energy conducted via supply circuitry;

using bias circuitry, biasing the supply circuitry to cause the supply circuitry to conduct the electrical energy used to generate the output signal;

conducting electrical energy via dynamic circuitry to provide the transitions in the output signal as a result of the transitions in the input signal; and

outputting the output signal in the second voltage domain different than the first voltage domain.

25. The method of claim 24 wherein the supply circuitry conducts the electrical energy in parallel with the electrical energy conducted by the dynamic circuitry.

26. The method of claim 25 further comprising limiting an amount of the electrical energy conducted via the supply circuitry.

27. The method of claim 24 wherein the generating comprises charging an output node using the electrical energy conducted via the supply circuitry and the electrical energy conducted via the dynamic circuitry.

28. The method of claim 27 further comprising selectively grounding the output node and isolating the output node from ground to provide the transitions in the output signal.

29. A level shifting method comprising:

receiving an input signal at an input, the input signal being in a first voltage domain and having a plurality of transitions;

charging an output node using electrical energy;

outputting an output signal using electrical energy at the output node, the output signal being within a second voltage domain different than the first voltage domain and having a plurality of transitions corresponding to the transitions in the input signal; and

wherein the charging comprises charging the output node using the electrical energy which is conducted via a plurality of parallel charging devices from a common source during the transitions in the output signal.

30. The method of claim 29 wherein the charging comprises charging the output node using only one of the parallel charging devices after the transitions in the output signal.

31. The method of claim 30 wherein the one of the parallel charging devices limits an amount of the electrical energy provided to the output node during the charging.

32. The method of claim 30 further comprising conducting electrical energy using another of the charging devices as a result of the transitions in the input signal.

33. The method of claim 29 wherein the outputting comprises inverting the electrical energy at the output node.