Timing advance enhancements for cellular communications

• US 9,332,511 B2
• Filed: 09/17/2014
• Issued: 05/03/2016
• Est. Priority Date: 03/12/2010
• Status: Active Grant

• Current Assignee: Malikie Innovations Limited (Key Patent Innovations Limited)
• Original Assignee: Blackberry Limited
• Inventors: Hole, David Philip, Borsella, Remo, Faurie, Rene, Venkob, Satish, Hanov, Steven Michael, Kreuzer, Werner Karl
• Primary Examiner(s): Sheikh, Ayaz
• Assistant Examiner(s): Ghafoerkhan, Faiyazkhan
• Application Number:
  US14/488,484
• Publication Number:
  US 20150003430A1
• Time in Patent Office: 594 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04W 56/0005 synchronizing of arrival of multiple uplinks
• CPC Class Codes: H04W 56/0045 compensating for timing error by altering transmission time
• CPC Class Codes: H04W 74/0833 Random access procedures, e.g. with 4-step access
• CPC Class Codes: H04W 74/0866 using a dedicated channel for access

Abstract

A disclosed example method involves, when a device is operating in a stationary mode and before a need of the device to communicate data, determining whether a stored timing advance is valid. When the stored timing advance is not valid, a valid timing advance is determined before the need of the device to communicate the data.

Claims

1. A method comprising:

when a device is operating in a stationary mode and before a need of the device to communicate data, determining whether a stored timing advance is valid, wherein determining whether the stored timing advance is valid includes determining if a pre-determined time interval has elapsed since a last successful data transfer, whether a pre-determined number of attempts to access a network have failed when the device is in the stationary mode, and whether the device has moved; and

in response to the stored timing advance being invalid, transmitting an access burst over a random access channel to determine a valid timing advance before the need of the device to communicate the data.

2. The method as defined in claim 1, further comprising, when the stored timing advance is valid, communicating the data using the stored timing advance.

3. The method as defined in claim 1 further comprising:

after determining the valid timing advance, using the valid timing advance for a subsequent data transfer.

4. An apparatus comprising:

a processor configured to;

when a device is operating in a stationary mode and before a need of the device to communicate data, determine whether a stored timing advance is valid, wherein determining whether the stored timing advance is valid includes determining if a pre-determined time interval has elapsed since a last successful data transfer, whether a pre-determined number of attempts to access a network have failed when the device is in the stationary mode, and whether the device has moved; and

in response to the stored timing advance being invalid, transmit an access burst over a random access channel to determine a valid timing advance before the need of the device to communicate the data.

5. The apparatus as defined in claim 4, wherein the processor is further configured to, when the stored timing advance is valid, cause the device to communicate the data using the stored timing advance.

6. The apparatus as defined in claim 4 further comprising:

after determining the valid timing advance, using the valid timing advance for a subsequent data transfer.

7. A computer readable storage memory having instructions stored thereon that, when executed, cause a machine to at least:

when a device is operating in a stationary mode and before a need of the device to communicate data, determine whether a stored timing advance is valid, wherein determining whether the stored timing advance is valid includes determining if a pre-determined time interval has elapsed since a last successful data transfer, whether a pre-determined number of attempts to access a network have failed when the device is in the stationary mode, and whether the device has moved; and

in response to the stored timing advance being invalid, transmit an access burst over a random access channel to determine a valid timing advance before the need of the device to communicate the data.

8. The computer readable storage memory as defined in claim 7, wherein the instructions further cause the machine to, when the stored timing advance is valid, cause the device to communicate the data using the stored timing advance.

9. The computer readable storage memory as defined in claim 7 further comprising:

after determining the valid timing advance, using the valid timing advance for a subsequent data transfer.