Memory device for reducing a write fail, a system including the same, and a method thereof

• US 9,335,951 B2
• Filed: 08/29/2013
• Issued: 05/10/2016
• Est. Priority Date: 08/29/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Jong Pil, Park, Chul Woo, Yu, Hak Soo, Hwang, Hong Sun
• Primary Examiner(s): Mamo, Elias
• Application Number:
  US14/013,275
• Publication Number:
  US 20140068203A1
• Time in Patent Office: 985 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0676 Magnetic disk device
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

Claims

1. A memory system comprising:

a memory device comprising a plurality of memory cells; and

a memory controller configured to issue a plurality of write commands on the memory device,

wherein the memory device performs a first write operation corresponding to a last write command of the plurality of write commands to write a data set to first memory cells, performs a precharge operation, and then, performs a second write operation corresponding to the last write command to rewrite the data set to the first memory cells, and

wherein the first write operation and the second write operation are writing the same data set to the first memory cells of the plurality of memory cells having a same address,

wherein the memory controller is configured to further issue at least one read command or at least one write command after the precharge command and before the second write operation,

wherein the memory device sends an alarm signal to the memory controller and the memory controller, in response to the alarm signal, applies the last write command to the memory device after the precharge command.

2. The memory system of claim 1, wherein the memory controller comprises:

an arbiter configured to;

receive a plurality of write requests from a host;

generate the active command, the plurality of write commands, and the precharge command;

store the plurality of write commands in a queue; and

schedule the commands stored in the queue according to a scheduling algorithm.

3. The memory system of claim 2,

wherein the queue comprises:

a write queue configured to store the plurality of write commands; and

a read queue configured to store the at least one read command.

4. The memory system of claim 3,

wherein the memory controller, after the first write operation, retains the last write command in the write queue and issues the last write command for the second write operation.

5. The memory system of claim 1, wherein the memory device further comprises an event detector configured to detect whether the precharge command is issued, and the memory device generates the alarm signal according to a result of the detection.

6. The memory system of claim 1,

wherein the memory device executes at least one read command or at least one write command after the precharge command and before the second write operation without intervention of the memory controller.

7. The memory system of claim 6,

wherein the memory device further comprises a write queue configured to store the plurality of write commands received from the memory controller.

8. The memory system of claim 7,

wherein the memory device, after the first write operation in response to the last write command, retains the last write command in the write queue to perform, in response to the last write command, the second write operation after the precharge command.

9. The memory system of claim 8,

wherein the memory device sends to the memory controller a state signal indicating that the second write operation is being executed.

10. The memory system of claim 1,

wherein the memory controller schedules write commands having a same row address to be executed sequentially from the plurality of write commands.

11. The memory system of claim 1,

wherein the memory controller schedules write commands having a same bank address and a same row address to be executed sequentially from the plurality of write commands.

12. A method of writing data to a memory device, the method comprising:

activating a word line in a memory bank in response to an active command;

continuously writing a plurality of data sets to memory cells associated with the word line in response to a corresponding write command of a plurality of write commands;

precharging the word line after a last write command of the plurality of write commands is performed; and

writing, in response to the last write command, the last data set to the memory cells after the precharge command; and

executing at least one read command or at least one write command after the precharge command and before the last write command issued after the precharge command,

wherein the last write command after the precharge command is performed in response to the alarm signal from the memory device.

13. The method of claim 12, further comprising storing a plurality of write commands received from a memory controller in a write queue.

14. The method of claim 13, further comprising:

removing a write command executed from the plurality of write commands stored in the write queue, wherein the last write command is retained after the precharge command and is executed after the precharge command.

15. The method of claim 12,

wherein the precharging is performed in response to a precharge command issued from a memory controller or an internally generated precharge command in the memory device.