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Memory device for reducing a write fail, a system including the same, and a method thereof

  • US 9,335,951 B2
  • Filed: 08/29/2013
  • Issued: 05/10/2016
  • Est. Priority Date: 08/29/2012
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a memory device comprising a plurality of memory cells; and

    a memory controller configured to issue a plurality of write commands on the memory device,wherein the memory device performs a first write operation corresponding to a last write command of the plurality of write commands to write a data set to first memory cells, performs a precharge operation, and then, performs a second write operation corresponding to the last write command to rewrite the data set to the first memory cells, andwherein the first write operation and the second write operation are writing the same data set to the first memory cells of the plurality of memory cells having a same address,wherein the memory controller is configured to further issue at least one read command or at least one write command after the precharge command and before the second write operation,wherein the memory device sends an alarm signal to the memory controller and the memory controller, in response to the alarm signal, applies the last write command to the memory device after the precharge command.

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