Universal serial bus device and charging and enumeration method

• US 9,336,170 B2
• Filed: 02/22/2011
• Issued: 05/10/2016
• Est. Priority Date: 05/11/2010
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Hong, Hao-Ping, Chen, Shang-Ping, Shen, Ding-Shiuan
• Primary Examiner(s): Dunn, Drew A
• Assistant Examiner(s): Chung, Steve T
• Application Number:
  US13/031,616
• Publication Number:
  US 20110279095A1
• Time in Patent Office: 1,904 Days
• Field of Search: 320/103, 320/106, 320/107, 320/111, 320/114, 320/115, 320/164
• US Class Current: 1/1
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/0045 concerning the insertion or the connection of the batteries
• CPC Class Codes: H02J 7/0068 Battery or charger load switching, e.g. concurrent charging and load supply H02J7/0013 takes precedence
• CPC Class Codes: H02J 7/007184 in response to battery voltage gradient

Abstract

A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for providing a voltage source having a predetermined voltage to one of the first pin and the second pin and for providing a current source having a predetermined current to the other of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the predetermined voltage and the predetermined current substantially intact when an external charger charges a battery device of the universal serial bus device.

Claims

1. A universal serial bus (USB) device, comprising:

a core circuit, having a first pin and a second pin, the core circuit having an input impedance looking into the core circuit from the first pin and the second pin; and

a charging control circuit, coupled to the core circuit, comprising;

a voltage source, arranged for selectively coupling to one of the first pin and the second pin according to a switch control signal;

wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin, and the input impedance is configurable according to the switch control signal;

wherein the USB device is further coupled to an external charger and a battery device; and

when the USB device is under a dead battery condition, the external charger provides a first supply voltage to the battery device to charge the battery device to make the battery device generate a battery output voltage, and the core circuit is arranged to be powered up by a second supply voltage derived from the battery output voltage generated by the battery device, rather than derived from the first supply voltage; and

the switch control signal is generated in response to the second supply voltage.

2. The USB device of claim 1, wherein the first pin and the second pin are arranged to be permanently coupled to the core circuit.

3. The USB device of claim 1, wherein when the first pin and the second pin have floating voltages, the input impedance of the core circuit resists a current to flow into the core circuit.

4. The USB device of claim 1, wherein the charging control circuit further selectively provides a current source to one of the first pin and the second pin, and the input impedance of the core circuit is configured to make the current source substantially intact when the current source is coupled to one of the first pin and the second pin.

5. The USB device of claim 1, wherein the charging control circuit further selectively provides a resistor to one of the first pin and the second pin.

6. The USB device of claim 1, wherein when the USB device is under the dead battery condition, the input impedance of the core circuit is configured to make the predetermined voltage and the predetermined current substantially intact.

7. The USB device of claim 1, wherein the first supply voltage and the second supply voltage are respectively available to the charging control circuit and the core circuit when the charging control circuit operates.

8. The USB device of claim 1, wherein the first supply voltage is available to the charging control circuit and the second supply voltage is not available to the core circuit when the charging control circuit operates.

9. The USB device of claim 1, wherein the charging control circuit comprises:

a charger controller, arranged for generating a control signal;

a charger detector, arranged for providing the voltage source; and

a switch circuit, coupled to the first pin and the second pin in parallel, the switch circuit arranged for selectively coupling the voltage source to one of the first pin and the second pin.

10. The USB device of claim 9, wherein the control signal is generated in response to the first supply voltage.

11. The USB device of claim 10, wherein when the charging control circuit is powered by the first supply voltage, the charging control circuit generates the control signal.

12. The USB device of claim 1, wherein when the core circuit is powered up by the second supply voltage, the core circuit generates the switch control signal.

14. The USB device of claim 1, wherein the core circuit comprises:

a control circuit, arranged for receiving a core voltage and generating the switch control signal; and

a physical layer circuit, having the first pin and the second pin, the physical layer circuit arranged for being configured by the switch control signal and powered by the core voltage.

15. The USB device of claim 1, further comprising a start-up circuit coupled to the core circuit and the charging control circuit, the start-up circuit arranged for generating a start-up ready signal for indicating the dead battery condition of the USB device.

16. The USB device of claim 1, further comprising a converting circuit arranged for receiving the battery output voltage to provide a core voltage to power up the core circuit.

17. The USB device of claim 16, further comprising a control circuit arranged for receiving the battery output voltage and generating a control signal to enable the converting circuit.

13. A universal serial bus (USB) device, comprising:

a core circuit, having a first pin and a second pin, the core circuit having an input impedance looking into the core circuit from the first pin and the second pin; and

a charging control circuit, coupled to the core circuit, comprising;

a voltage source, arranged for selectively coupling to one of the first pin and the second pin according to a switch control signal;

wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin, and the input impedance is configurable according to the switch control signal;

wherein the USB device is further coupled to an external charger and a battery device; and

when the USB device is under a dead battery condition, the external charger provides a first supply voltage to the battery device to charge the battery device to make the battery device generate a battery output voltage, and the core circuit is arranged to be powered up by a second supply voltage derived from the battery output voltage generated by the battery device, rather than derived from the first supply voltage;

wherein the core circuit comprises;

a first P-type transistor, having an output node coupled to the first pin; and

a second P-type transistor, having an output node coupled to the second pin;

wherein a control node of the first P-type transistor and a control node of the second P-type transistor are tied to the second supply voltage, resulting in the input impedance.

18. A bus interfacing device, comprising:

a start-up circuit, arranged for generating a start-up ready signal;

a first control circuit, arranged for receiving a battery output voltage and generating a first control signal according to the start-up ready signal;

a converting circuit, arranged for receiving the battery output voltage to provide a core voltage according to the first control signal;

a second control circuit, arranged for receiving the core voltage and generating a second control signal according to the start-up ready signal;

a physical layer circuit, having a first pin and a second pin, the physical layer circuit arranged for being configured by the second control signal and powered by the core voltage, and the physical layer circuit having an input impedance looking into the physical layer circuit from the first pin and the second pin; and

a charging control circuit, comprising;

a charger detector, arranged for generating a predetermined voltage; and

a switching circuit, arranged for selectively coupling the predetermined voltage to one of the first pin and the second pin according to a switch control signal;

wherein the input impedance of the physical layer circuit is configurable according to the second control signal to make the predetermined voltage substantially intact when the predetermined voltage is coupled to one of the first pin and the second pin; and

the bus interfacing device is further coupled to an external charger and a battery device; and

when the bus interfacing device is under a dead battery condition, the external charger provides a first supply voltage to the battery device to charge the battery device to make the battery device generate the battery output voltage, and the second control circuit and the physical layer circuit are arranged to be powered up by the core voltage derived from the battery output voltage generated by the battery device, rather than derived from the first supply voltage; and

the switch control signal is generated in response to the core voltage.

19. The bus interfacing device of claim 18, wherein the first pin and the second pin are arranged to be permanently coupled to the physical layer circuit.

20. The bus interfacing device of claim 18, wherein the charger detector further generates a predetermined current, and the switching circuit further selectively coupling the predetermined current to one of the first pin and the second pin, and the input impedance of the physical layer circuit is configured to make the predetermined current substantially intact when the predetermined current is coupled to one of the first pin and the second pin.

21. The bus interfacing device of claim 18, wherein when the bus interfacing device is under the dead battery condition, the input impedance of the physical layer circuit is configured to make the predetermined voltage substantially intact.

22. A bus interfacing device, comprising:

a start-up circuit, arranged for generating a start-up ready signal;

a converting circuit, arranged for receiving a battery output voltage to provide a core voltage;

a core circuit, having a first pin and a second pin, the core circuit arranged for being configured according to the start-up ready signal and powered by the core voltage, and the core circuit having an input impedance looking into the core circuit from the first pin and the second pin; and

a charging control circuit, comprising;

a charger detector, arranged for generating a predetermined voltage; and

a switching circuit, arranged for selectively coupling the predetermined voltage to one of the first pin and the second pin according to a switch control signal;

wherein the input impedance of the core circuit is configurable according to the start-up ready signal to make the predetermined voltage substantially intact when the predetermined voltage is coupled to one of the first pin and the second pin; and

the bus interfacing device is further coupled to an external charger and a battery device; and

when the bus interfacing device is under a dead battery condition, the external charger provides a first supply voltage to the battery device to charge the battery device to make the battery device generate the battery output voltage, and the core circuit is arranged to be powered up by the core voltage derived from the battery output voltage generated by the battery device, rather than derived from the first supply voltage; and

the switch control signal is generated in response to the core voltage.

23. The bus interfacing device of claim 22, wherein the first pin and the second pin are arranged to be permanently coupled to the core circuit.

24. The bus interfacing device of claim 22, wherein when the bus interfacing device is under the dead battery condition, the input impedance of the physical layer circuit is configured to make the predetermined voltage substantially intact.

25. A method for bus interfacing:

providing a core circuit having a first pin and a second pin;

selectively providing a voltage source having a predetermined voltage to one of the first pin and the second pin according to a switch control signal; and

arranging an input impedance looking into the core circuit from the first pin and the second pin to make the predetermined voltage substantially intact when the voltage source is coupled to one of the first pin and the second pin;

wherein the input impedance is configurable according to the switch control signal;

wherein the method is applied to a USB device, and when the USB device is under a dead battery condition, a battery device receives a first supply voltage from an external charger to generate a battery output voltage, and the core circuit is arranged to be powered up by a second supply voltage derived from the battery output voltage generated by the battery device, rather than derived from the first supply voltage; and

the switch control signal is generated in response to the second supply voltage.

26. The method of claim 25, further comprising:

selectively providing a current source having a predetermined current to one of the first pin and the second pin; and

arranging the input impedance to make the predetermined current substantially intact when the current source is coupled to one of the first pin and the second pin.

27. The method of claim 25, wherein the first pin and the second pin are arranged to be permanently coupled to the core circuit.