Method of forming layout design
First Claim
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1. A method of forming a layout design for fabricating an integrated circuit (IC), the method comprising:
- identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and
generating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern of the set of layout patterns having a width measurable along the second direction, and the width of the first layout pattern being less than twice the predetermined pitch.
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Abstract
A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.
15 Citations
20 Claims
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1. A method of forming a layout design for fabricating an integrated circuit (IC), the method comprising:
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identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and generating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern of the set of layout patterns having a width measurable along the second direction, and the width of the first layout pattern being less than twice the predetermined pitch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a layout design for fabricating an integrated circuit (IC), the method comprising:
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identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and generating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern and a second layout pattern of the set of layout patterns being separated by a first gap along the second direction, and a width of the first gap measurable along the second direction being less than twice the predetermined pitch. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A layout design for fabricating an integrated circuit (IC), comprising:
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a first layout layer, comprising a plurality of gate structure layout patterns, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and a second layout layer, comprising a set of mask layout patterns arranged based on one or more opening regions, the one or more opening regions overlapping one or more of the plurality of gate structure layout patterns corresponding to one or more gate structures subject to an electrical characteristic tuning process, a first mask layout pattern of the set of mask layout patterns having a width measurable along the second direction, and the width of the first mask layout pattern being equal to the predetermined pitch. - View Dependent Claims (20)
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Specification