×

Method of forming layout design

  • US 9,336,348 B2
  • Filed: 09/12/2014
  • Issued: 05/10/2016
  • Est. Priority Date: 09/12/2014
  • Status: Active Grant
First Claim
Patent Images

1. A method of forming a layout design for fabricating an integrated circuit (IC), the method comprising:

  • identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and

    generating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern of the set of layout patterns having a width measurable along the second direction, and the width of the first layout pattern being less than twice the predetermined pitch.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×