Microprocessor including a display interface in the microprocessor

• US 9,336,752 B1
• Filed: 12/21/2007
• Issued: 05/10/2016
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation), Sun Microsystems Technology Ltd. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Glaskowsky, Peter N.
• Primary Examiner(s): Merouan, Abderrahim
• Application Number:
  US11/963,579
• Time in Patent Office: 3,063 Days
• Field of Search: 345/156, 345/519, 710/5, 710/163, 711/1, 711/103, 711/108, 711/115
• US Class Current: 1/1
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Claims

1. A processing system comprising:

a single processor comprising a first integrated circuit,

wherein the first integrated circuit comprises a processor core, a display interface, and a memory controller coupled to a first bus interface, and

wherein the display interface is adapted to display graphical information generated by a graphics engine that is not on the first integrated circuit; and

a second bus interface for allowing communication with the first integrated circuit via the first bus interface, wherein the second bus interface is adapted to allow for communications with the graphics engine,

wherein the processor core of the first integrated circuit performs at least some of the functions of the graphics engine when the graphics engine is disabled.

2. The processing system of claim 1 that comprises a second integrated circuit, wherein the second integrated circuit includes:

at least one I/O device coupled to the second bus interface.

3. The processing system of claim 2 wherein the graphics engine is internal to the second integrated circuit.

4. The processing system of claim 2 wherein the graphics engine is external to the second integrated circuit.

5. The processing system of claim 2, further comprising a third integrated circuit, wherein the third integrated circuit includes a graphics engine that communicates with the first integrated circuit.

6. The processing system of claim 1 wherein the graphics engine is coupled to at least one of a second display and a second memory.

7. The processing system of claim 1 wherein the processor core of the first integrated circuit performs at least some of the functions of the graphics engine when the graphics engine is disabled for 2-D only display operations.

8. The processing system of claim 1 wherein the first integrated circuit further comprises a CRT controller function.

9. The processing system of claim 8, wherein the CRT controller function is within the display interface.

10. The processing system of claim 8, wherein the CRT controller function is capable of performing compositing operations.

11. A method within a processing system;

the processing system comprising a single processor comprising a first integrated circuit and a bus interface in communication with the first integrated circuit, the method comprising;

providing a processor core, a display interface and a memory controller in the first integrated circuit, wherein the memory controller interfaces to a first memory;

allowing a graphics engine to communicate with the bus interface;

wherein the graphics engine interfaces to a second memory; and

transferring graphics data from the second memory to the first memory via the bus interface,

wherein the processor core of the first integrated circuit performs at least some of the functions of the graphics engine when the graphics engine is disabled.

12. The method of claim 11, wherein the graphics data is copied from the second to the first memory by the bus interface while the data is being sent by the graphics engine to the display interface.

13. A processing system comprising:

a single processor comprising a first integrated circuit that comprises a processor core, a display interface, and a memory controller coupled to a first bus interface,

wherein the first integrated circuit further comprises a CRT controller function, and wherein the memory controller is adapted to be coupled to a memory; and

a second integrated circuit in communication with the first integrated circuit that comprises a second bus interface; and

at least one I/O device coupled to the second bus interface,

wherein the second bus interface allows communication with the first integrated circuit via the first bus interface and is adapted to allow for communication to a graphics engine,

wherein the processor core of the first integrated circuit performs at least some of the functions of the graphics engine when the graphics engine is disabled.

14. The processing system of claim 13 wherein the CRT controller function is capable of performing compositing operations.

15. A non-transitory computer readable medium that comprises a description of a processing system and where the processing system comprises:

a single processor comprising a first integrated circuit that comprises a processor core, a display interface, and a memory controller coupled to a first bus interface,

wherein the display interface is adapted to display graphical information generated by a graphics engine that is not on the first integrated circuit; and

a second bus interface for allowing communication with the first integrated circuit via the first bus interface and adapted to allow for communications with the graphics engine,

wherein the processor core of the first integrated circuit performs at least some of the functions of the graphics engine when the graphics engine is disabled.

16. The computer readable medium of claim 15 wherein the first integrated circuit further comprises a CRT controller function.

17. The computer readable medium of claim 16, wherein the CRT controller function is within the display interface.

18. The computer readable medium of claim 16, wherein the CRT controller function is capable of performing compositing operations.

19. The computer readable medium of claim 15, wherein the processor core can perform at least some of the functions of the graphics engine and the graphics engine can be disabled.

20. A processing system comprising:

a single processor comprising a first integrated circuit that comprises means for processing instructions, means for interfacing to a display, and means for controlling a memory coupled to first means for interfacing to a first bus,

wherein the display interfacing means is adapted to display graphical information generated by a graphics engine means that is not on the first integrated circuit; and

second means for interfacing to the first bus, further comprising means for allowing communication with the first integrated circuit via the first means for bus interfacing, and further adapted to allow for communications with the graphics engine means,

wherein the means for processing instructions performs at least some of the functions of the means for interfacing to a display when the means for interfacing to a display is disabled.