Non-volatile memory device having vertical structure and method of operating the same

• US 9,336,884 B2
• Filed: 06/11/2014
• Issued: 05/10/2016
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Jae-hun, Kim, Han-soo, Cho, Won-seok, Jang, Jae-hoon, Shim, Sun-il
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/302,025
• Publication Number:
  US 20140293703A1
• Time in Patent Office: 699 Days
• Field of Search: 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Claims

1. A non-volatile memory device having a vertical structure, the non-volatile memory device comprising:

a substrate;

a semiconductor pole formed on the substrate to extend vertically with respect to the substrate;

a NAND string formed on the substrate to extend vertically with respect to the substrate and along sidewalls of the semiconductor pole, the NAND string comprising a plurality of control gate electrodes arranged along with the sidewalls of the semiconductor pole and at least one set of at least two selection gate electrodes arranged along with the sidewalls of the semiconductor pole adjacent to the plurality of control gate electrodes,

wherein the at least one set of at least two selection gate electrodes has a first selection gate electrode and a second selection gate electrode;

at least one set of at least two selection lines, the one set of at least two selection lines having a first selection line and a second selection line; and

at least two contact plugs, the at least two contact plugs having a first contact plug connected between the first selection line and the first selection gate electrode and a second contact plug connected between the second selection line and the second selection gate electrode.

2. The non-volatile memory device of claim 1, wherein the at least one set of at least two selection gate electrodes is arranged farther than the plurality of control gate electrodes with respect to the substrate.

3. The non-volatile memory device of claim 1, wherein the at least one set of at least two selection gate electrodes is arranged closer than the plurality of control gate electrodes with respect to the substrate.

4. The non-volatile memory device of claim 1, wherein heights of the first contact plug and the second contact plug are different from each other.

5. The non-volatile memory device of claim 1, wherein the NAND string further comprises a plurality of storage media, wherein each of the plurality of storage media is interposed between the sidewalls of the semiconductor pole and each of the plurality of control gate electrodes, respectively, and

wherein each of the plurality of storage media comprises a tunneling insulating layer, a charge storing layer and a blocking insulating layer.

6. The non-volatile memory device of claim 1, wherein the NAND string further comprises a plurality of storage media, wherein each of the plurality of storage media is interposed between the sidewalls of the semiconductor pole and each of the plurality of control gate electrodes and between the sidewalls of the semiconductor pole and each of the at least two selection gate electrodes, respectively, and

wherein each of the plurality of storage media comprises a tunneling insulating layer, a charge storing layer and a blocking insulating layer.

7. The non-volatile memory device of claim 1, wherein the at least one set of at least two selection gate electrodes comprises one set of at least two string selection gate electrodes adjacent to the plurality of control gate electrodes and one set of at least two ground selection gate electrodes adjacent to the plurality of control gate electrodes opposite to the one set of at least two string selection electrodes.

8. The non-volatile memory device of claim 1, wherein a gate length of each of the control gate electrodes and a gate length of each of the selection gate electrodes are substantially equal.

17. The non-volatile memory device of claim 1, wherein a width of one portion of the semiconductor pole is greater than a width of another portion of the semiconductor pole.

9. A non-volatile memory device having a vertical structure, the non-volatile memory device comprising:

a substrate;

a semiconductor pole formed on the substrate to extend vertically with respect to the substrate;

a NAND string formed on the substrate to extend vertically with respect to the substrate and along sidewalls of the semiconductor pole, the NAND string comprising a plurality of control gate electrodes arranged along with the sidewalls of the semiconductor pole and at least one set of at least two selection gate electrodes arranged along with the sidewalls of the semiconductor pole over the plurality of control gate electrodes to the substrate;

at least two contact plugs extending vertically with respect to the substrate; and

at least two selection lines farther than the NAND string with respect to the substrate, wherein each of the at least two selection lines is connected to each of the at least two selection gate electrodes via each of the at least two selection contact plugs, respectively, wherein the at least two selection contact plugs have different height.

10. The non-volatile memory device of claim 9, further comprising:

a bit line connected to a first end of the NAND string; and

a common source line connected to a second end of the NAND string proximate to the substrate and opposite to the bit line.

11. The non-volatile memory device of claim 10, wherein the at least one set of at least two selection gate electrodes is arranged between the bit line and the plurality of control gate electrodes.

12. The non-volatile memory device of claim 10, wherein the at least one set of at least two selection gate electrodes is arranged between the common source line and the plurality of control gate electrodes.

13. The non-volatile memory device of claim 9, further comprising a plurality of word lines farther than the NAND string with respect to the substrate and a plurality of control contact plugs extending vertically with respect to the substrate,

wherein each of the plurality of control gate electrodes is connected to each of the plurality of word lines via each of the plurality of control contact plugs, respectively.

14. The non-volatile memory device of claim 13, wherein the plurality of control contact plugs have different heights.

18. The non-volatile memory device of claim 9, wherein a width of one portion of the semiconductor pole is greater than a width of another portion of the semiconductor pole.

15. A non-volatile memory device having a vertical structure, the non-volatile memory device comprising:

a substrate;

a semiconductor pole formed on the substrate to extend vertically with respect to the substrate; and

a NAND string formed on the substrate to extend vertically with respect to the substrate and along sidewalls of the semiconductor pole, the NAND string comprising a plurality of control gate electrodes arranged along with the sidewalls of the semiconductor pole and one set of at least two selection gate electrodes arranged along with the sidewalls of the semiconductor pole over the plurality of control gate electrodes with respect to the substrate,

wherein the NAND string further comprises one set of at least two selection transistors, and each of the at least two selection transistors comprises each of the at least two selection gate electrodes, and

wherein the at least two selection transistors have different channel width.

16. The non-volatile memory device of claim 15, wherein a width of an upper portion of the semiconductor pole is greater than a width of a lower portion of the semiconductor pole.

19. The non-volatile memory device of claim 15, wherein a width of one portion of the semiconductor pole is greater than a width of another portion of the semiconductor pole.