Non-volatile memory devices and methods of manufacturing the same

• US 9,336,888 B2
• Filed: 05/01/2015
• Issued: 05/10/2016
• Est. Priority Date: 09/04/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Heo, Hyun
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US14/702,358
• Publication Number:
  US 20150235708A1
• Time in Patent Office: 375 Days
• Field of Search: 365/148, 365/185.12, 365/185.22, 365/185.05
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.

Claims

1. A nonvolatile memory device, comprising:

a memory cell array configured to comprises a plurality of strings;

a page buffer unit connected to the plurality of strings, respectively, and configured to sense data;

a switching unit configured to comprise a variable resistor for performing a switching operation depending on whether an erase operation of the memory cell array is performed or not; and

a page buffer protection unit configured to protect the page buffer unit.

2. The nonvolatile memory device according to claim 1, wherein the switching unit comprises:

a lower electrode;

a variable resistance unit formed over the lower electrode; and

an upper electrode formed over the variable resistance unit.

3. The nonvolatile memory device according to claim 2, wherein the variable resistance unit is formed of a unipolar device.

4. The nonvolatile memory device according to claim 3, wherein the unipolar device has a low voltage characteristic in a reset voltage or lower, has a high voltage characteristic when the reset voltage or higher is applied, and has a low voltage characteristic again when a set voltage or higher.

5. The nonvolatile memory device according to claim 4, wherein the unipolar device is made of any one of NiO, MnOx, ZrO₂, (Ba, Sr)TiO₃, MgZnO, and HfO₂.

6. The nonvolatile memory device according to claim 1, wherein the page buffer unit is formed of a low voltage transistor.

7. The nonvolatile memory device according to claim 1, wherein the page buffer protection unit is formed of a resistor or a capacitor.

8. The nonvolatile memory device according to claim 2, wherein the lower electrode, variable resistance unit, and the upper electrode are formed in a peripheral region of the memory cell array.

9. The nonvolatile memory device according to claim 1, wherein the page buffer unit comprises a bit line selection unit and a latch unit.

10. The nonvolatile memory device according to claim 9, wherein the bit line selection unit comprises NMOS transistors.

11. The nonvolatile memory device according to claim 1, wherein the switching operation is turned off when the erase operation is performed.

12. The nonvolatile memory device according to claim 1, wherein the switching operation is turned on when the erase operation is not performed.

13. The nonvolatile memory device according to claim 1, wherein the switching operation is turned on when a program operation or a read operation is performed.