Memory device including nonvolatile memory cell

• US 9,336,894 B2
• Filed: 06/29/2015
• Issued: 05/10/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Hyun-Min, Maeda, Shigenobu, Yoon, Ji-Hoon
• Primary Examiner(s): Le, Vu
• Application Number:
  US14/753,620
• Publication Number:
  US 20160093398A1
• Time in Patent Office: 316 Days
• Field of Search: 365/103, 365/104, 365/94, 257/315, 257/316, 257/321
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate

Abstract

A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.

Claims

1. A memory device including nonvolatile memory cells, each of which comprises:

an active pattern including first to fourth regions successively arranged in one direction;

a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; and

a second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer,

wherein the nonvolatile memory cell is configured such that;

a first voltage is applied to the second gate electrode when the second insulating layer is in a first state such that a current that passes through the second region becomes a first current,

the first voltage is applied to the second gate electrode when the second insulating layer is in a second state such that a current that passes through the second region becomes a second current,

the first voltage is applied to the second gate electrode when the second insulating layer is in a third state such that a current that passes through the second region becomes a third current,

the second current and the third current are higher than the first current, and

the second current is different from the third current.

2. The memory device of claim 1, wherein if the nonvolatile memory cell is a One-Time Programmable (OTP) cell, the first state is a state before the second insulating layer is programmed, and

wherein if the nonvolatile memory cell is a Multi-Time Programmable (MTP) cell, the first state is a state before the second insulating layer is formed.

3. The memory device of claim 2, an area of each of the first and second gate electrodes of the OTP cell overlapping the active pattern is greater than an area of each of the first and second gate electrodes of the MTP cell overlapping the active pattern.

4. The memory device of claim 2, wherein the second state of the OTP cell does not change to the first state, and

wherein the second and third states of the MTP cell are changeable with each other.

5. The memory device of claim 4, wherein the second state is changed to the third state by applying a second voltage to the second gate electrode, and

wherein the third state is changed to the second state by applying a third voltage equal to or less than the second voltage to the second gate electrode.

6. The memory device of claim 1, wherein if the nonvolatile memory cell is a One-Time Programmable (OTP) cell, the second state is a state where the second insulating layer is programmed by a second voltage that is applied to the second gate electrode and is higher than the first voltage.

7. The memory device of claim 6, wherein the second insulating layer comprises an interface layer and a high-k dielectric layer that are successively formed on the active pattern, and

wherein the second state occurs by a breakdown at the interface layer in the second state.

8. The memory device of claim 1, wherein if the nonvolatile memory cell is a Multi-Time Programmable (MTP) cell, the second state is a state where the second insulating layer is set or formed by a second voltage that is applied to the second gate electrode and is higher than the first voltage, and the third state is a state where the second insulating layer is reset by a third voltage that is applied to the second gate electrode and is higher than the first voltage and is lower than the second voltage, and

wherein the second current is higher than the third current.

9. The memory device of claim 8, wherein the second insulating layer comprises an interface layer and a high-k dielectric layer that are successively formed on the active pattern, and

wherein a breakdown does not occur at the interface layer in the second state or the third state.

10. The memory device of claim 1, further comprising:

an interlayer insulating layer including a first trench and a second trench and formed on the active pattern,

wherein the first insulating layer includes a first interface layer formed on a bottom surface of the first trench and a first high-k insulating layer formed on the first interface layer along side surfaces and the bottom surface of the first trench, and

wherein the second insulating layer includes a second interface layer formed on a bottom surface of the second trench and a second high-k insulating layer formed on the second interface layer along side surfaces and the bottom surface of the second trench.

11. A memory device including nonvolatile memory cells, each of which comprises:

an active pattern including first to fourth regions successively arranged in one direction;

a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; and

a second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer,

wherein the first region is connected to a sense amplifier that detects a current passing through the second region,

wherein if the nonvolatile memory cell is a One-Time Programmable (OTP) cell before the second insulating layer is programmed or is a Multi-Time Programmable (MTP) cell before the second insulating layer is formed, the second insulating layer has a first resistance value,

wherein if the nonvolatile memory cell is the OTP cell, the second insulating layer has a second resistance value that is smaller than the first resistance value in the nonvolatile memory cell that is in a programmed state, and

wherein if the nonvolatile memory cell is the MTP cell, the second insulating layer has a third resistance value that is smaller than the first resistance value and is larger than the second resistance value in the nonvolatile memory cell that is in a set state.

12. The memory device of claim 11, wherein the set state of a nonvolatile memory cell occurs when a first voltage is applied to the second gate electrode, and

wherein a reset state of a nonvolatile memory cell occurs and the second insulating layer has a fourth resistance value greater than the third resistance value and smaller than the first resistance value, when a second voltage lower than the first voltage is applied to the second gate electrode.

13. The memory device of claim 11, wherein if the nonvolatile memory cell is the MTP cell, the second insulating layer has a fourth resistance value smaller than the first resistance value and greater than the third resistance value of the nonvolatile memory cell that is in a reset state,

wherein when a read voltage is applied to the second gate electrode to read a data that is written in the nonvolatile memory cell, a current that flows through the second insulating layer having the first resistance value becomes a first current, a current that flows through the second insulating layer having the second resistance value becomes a second current, a current that flows through the second insulating layer having the third resistance value becomes a third current, and a current that flows through the second insulating layer having the fourth resistance value becomes a fourth current, and

wherein a ratio of the second current to the first current is higher than a ratio of the third current to the fourth current.

14. A memory device comprising:

a row decoder configured to select a word line of a plurality of word lines;

a column decoder configured to select a bit line of a plurality of bit lines;

a first set of memory cells connected to corresponding word lines of the plurality of word lines and corresponding bit lines of the plurality of bit lines, each memory cell of the first set of memory cells having a first state and a second state opposite to the first state; and

a second set of memory cells connected to corresponding word lines of the plurality of word lines and corresponding bit lines of the plurality of bit lines, each memory cell of the second set of memory cells having a third state and a fourth state opposite to the third state,

wherein a first memory cell of the first set of memory cells having a first resistance value has the first state and a second memory cell of the first set of memory cells having a second resistance value less than the first resistance value has the second state, and

wherein a first memory cell of the second set of memory cells having a third resistance value less than the first resistance value and greater than the second resistance value has the third state, and a second memory cell of the second set of memory cells having a fourth resistance value less than the third resistance value and greater than the second resistance value has the fourth state.

15. The memory device of claim 14, wherein the first and second memory cells of the first set of memory cells and the first and second memory cells of the second set of memory cells are connected to the same word line.

16. The memory device of claim 14, wherein each respective memory cell of the first and second sets of memory cells includes first and second transistors connected in series to each other,

wherein the first transistor includes a gate, a first end that is floating and a second end, and

wherein the second transistor includes a gate connected to a word line of the plurality of the word lines, a first end and connected to the second end of the first transistor, and a second end connected to a bit line of the plurality of bit lines.

17. The memory device of claim 16, wherein the second memory cell of the first set of memory cells has the second state when a first voltage applied to the gate of the first transistor of the second memory cell,

wherein the first memory cell of the second set of memory cells has the third state when a second voltage less than the first voltage applied to the gate of the first transistor of the first memory cell of the second set of memory cells, and

wherein the second memory cell of the second set of memory cells has the fourth state when a third voltage less than the first voltage and greater than the second voltage applied to the gate of the first transistor of the second memory cell of the second set of memory cells.

18. The memory device of claim 17, wherein the gate of each of first and second transistors of each respective memory cell of the first and second sets of memory cells includes a first insulating layer, a second insulating layer formed on the first insulating layer, and a gate electrode formed on the second insulating layer,

wherein a conduction path is formed through first and second insulating layers of the first transistor of the second memory cell of the first set of memory cells,

wherein a conduction path is formed through a portion of the second insulation layer of the first transistor of the first memory cell of the second set of memory cells, the portion of the second insulation layer not entirely penetrating the second insulation layer in a column direction, and

wherein a conduction path is formed through the second insulating layer of the first transistor of the second memory cell of the second set of memory cells.

19. The memory device of claim 14, wherein the second state of the second memory cell of the first set of memory cells does not change to the first state, and

wherein the third and fourth states of the first and second memory cells of the second set of memory cells are changeable with each other.

20. The memory device of claim 19, wherein the third state of the first memory cell of the second set of memory cells is changed to the fourth state by applying a first voltage to the gate of the first transistor of the first memory cell of the second set of memory cells, and

wherein the fourth state of the second memory cell of the second set of memory cells is changed to the third state by applying a second voltage equal to or less than the first voltage to the gate of the first transistor of the second memory cell of the second set of memory cells.