Method of forming contact useful in replacement metal gate processing and related semiconductor structure

• US 9,337,094 B1
• Filed: 01/05/2015
• Issued: 05/10/2016
• Est. Priority Date: 01/05/2015
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Pranatharthiharan, Balasubramanian, Ok, Injo, Surisetty, Charan V. V. S.
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US14/589,222
• Time in Patent Office: 491 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66848 with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

A method of forming a contact is provided. The method may include forming a liner against a spacer around a gate; selectively removing an upper portion of the liner adjacent the spacer, forming a void; forming a spacer extension by filling the void with a spacer material; and forming a contact self-aligned to the spacer extension. A semiconductor structure is also disclosed. The structure may include: a gate; a spacer around the gate; a spacer extension extending laterally from an upper portion of the spacer; and a contact self-aligned to the spacer extension.

Claims

1. A method of forming a contact, comprising:

forming a liner against a spacer around a gate;

selectively removing an upper portion of the liner adjacent the spacer, forming a void;

forming a spacer extension by filling the void with a spacer material; and

forming a contact self-aligned to the spacer extension.

2. The method of claim 1, wherein the liner extends over a first interlayer dielectric (ILD) layer, further comprising forming a second ILD layer over the liner, wherein the second ILD layer is more polishing resistant than the first ILD layer.

3. The method of claim 2, wherein forming the second ILD layer includes forming a high density plasma (HDP) oxide layer over the liner.

4. The method of claim 2, wherein forming the liner includes forming the liner between a plurality of gates over the first ILD layer.

5. The method of claim 1, wherein the liner includes one of a high dielectric constant dielectric and titanium nitride (TiN).

6. The method of claim 1, wherein the gate includes a dummy gate, further comprising, prior to the selective removing:

removing the dummy gate; and

forming a metal gate in place of the dummy gate.

7. A method, comprising:

forming a liner against a spacer around a dummy gate;

removing the dummy gate;

forming a metal gate in place of the dummy gate;

selectively removing an upper portion of the liner adjacent the spacer, forming a void;

forming a spacer extension by filling the void with a spacer material; and

forming a contact self-aligned to the spacer extension.

8. The method of claim 7, wherein the liner extends over a first interlayer dielectric (ILD) layer over a substrate, further comprising forming a second ILD layer over the liner, wherein the second ILD layer is more polishing resistant than the first ILD layer.

9. The method of claim 8, wherein the second ILD layer forming includes forming a high density plasma (HDP) oxide layer over the liner.

10. The method of claim 8, wherein the liner forming includes forming the liner between a plurality of gates over the first ILD layer.

11. The method of claim 7, wherein the liner includes one of a high dielectric constant dielectric and titanium nitride (TiN).

12. A semiconductor structure comprising:

a gate;

a spacer around the gate;

a spacer extension extending laterally from an upper portion of the spacer;

a contact self-aligned to the spacer extension, and

a liner extending below the spacer extension.

13. The semiconductor structure of claim 12, wherein the liner extends laterally from the spacer.

14. The semiconductor structure of claim 13, further comprising a first interlayer dielectric (ILD) layer above a second ILD layer over a substrate, wherein the first ILD layer is more polishing resistant than the second ILD layer, and wherein the liner extends laterally between the first ILD layer and the second ILD layer.

15. The semiconductor structure of claim 14, wherein the first ILD layer includes a high density plasma (HDP) oxide and the second ILD layer includes a flowable chemical vapor deposition (FCVD) oxide layer.

16. The semiconductor structure of claim 12, wherein the gate includes a first gate positioned over a fin over a substrate and a second gate positioned on the substrate, and

wherein the liner extends laterally from the spacer of the first gate to the spacer of the second gate.

17. The semiconductor structure of claim 12, wherein the spacer extension includes a ledge extending from the spacer.

18. The semiconductor structure of claim 12, wherein the spacer and the spacer extension include a nitride.

19. The semiconductor structure of claim 12, wherein the gate includes a metal gate.