Capacitors within an interposer coupled to supply and ground planes of a substrate
First Claim
1. An apparatus, comprising:
- a first integrated circuit die and a second integrated circuit die;
an interposer coupled to the first integrated circuit die and the second integrated circuit die using a first plurality of interconnects, the interposer including an upper surface having at least one open space between the first integrated circuit die and the second integrated circuit die, the interposer including a lower surface having a second plurality of interconnects, the interposer including a first cross-sectional region beneath the first integrated circuit die and the second integrated circuit die and a second cross-sectional region beneath the at least one open space, the first and second cross-sectional regions being disjoint, the second cross-sectional region being devoid of any through substrate vias extending between the upper surface and the lower surface;
a substrate coupled to the interposer using the second plurality of interconnects;
wherein the substrate includes a supply voltage plane and a ground plane each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects;
wherein the interposer includes a plurality of capacitors entirely disposed in the second cross-sectional region, the plurality of capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects; and
wherein the plurality of capacitors of the interposer provide capacitance to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.
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Accused Products
Abstract
An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.
93 Citations
16 Claims
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1. An apparatus, comprising:
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a first integrated circuit die and a second integrated circuit die; an interposer coupled to the first integrated circuit die and the second integrated circuit die using a first plurality of interconnects, the interposer including an upper surface having at least one open space between the first integrated circuit die and the second integrated circuit die, the interposer including a lower surface having a second plurality of interconnects, the interposer including a first cross-sectional region beneath the first integrated circuit die and the second integrated circuit die and a second cross-sectional region beneath the at least one open space, the first and second cross-sectional regions being disjoint, the second cross-sectional region being devoid of any through substrate vias extending between the upper surface and the lower surface; a substrate coupled to the interposer using the second plurality of interconnects; wherein the substrate includes a supply voltage plane and a ground plane each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects; wherein the interposer includes a plurality of capacitors entirely disposed in the second cross-sectional region, the plurality of capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects; and wherein the plurality of capacitors of the interposer provide capacitance to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An apparatus, comprising:
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a first integrated circuit die including a first capacitor for providing a first capacitance; a second integrated circuit die; an interposer coupled to the first integrated circuit die and the second integrated circuit die using a first plurality of interconnects, the interposer including an upper surface having at least one open space between the first integrated circuit die and the second integrated circuit die, the interposer including a lower surface having a second plurality of interconnects, the interposer including a first cross-sectional region beneath the first integrated circuit die and the second integrated circuit die and a second cross-sectional region beneath the at least one open space, the first and second cross-sectional regions being disjoint, the second cross-sectional region being devoid of any through substrate vias extending between the upper surface and the lower surface; a substrate coupled to the interposer using the second plurality of interconnects; wherein the substrate includes a supply voltage plane and a ground plane coupled to the integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects; wherein the interposer includes a plurality of capacitors entirely disposed in the second cross-sectional region, the plurality of capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects; wherein the substrate includes a second capacitor coupled to the supply voltage plane and the ground plane for providing a second capacitance to the integrated circuit die through the interposer; and wherein a third capacitance from the plurality of capacitors of the interposer is provided to the integrated circuit die using the supply voltage plane and the ground plane of the substrate. - View Dependent Claims (15, 16)
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Specification