Hermetic wafer level packaging
First Claim
Patent Images
1. A method of packaging, comprising:
- providing a first wafer, wherein the first wafer contains a plurality of transistors and an interconnect structure having a plurality of metal layers that each contain a plurality of metal lines;
providing a second wafer, wherein the second wafer contains a micro-electrical-mechanical system (MEMS) device and a plurality of bonding pads, wherein the MEMS device includes at least one of;
actuators, mirrors, gyroscopes, or accelerometers; and
bonding the first wafer and the second wafer together through a metal diffusion process and in a manner such that the bonding pads of the second wafer are bonded to the interconnect structure of the first wafer.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
4 Citations
20 Claims
-
1. A method of packaging, comprising:
-
providing a first wafer, wherein the first wafer contains a plurality of transistors and an interconnect structure having a plurality of metal layers that each contain a plurality of metal lines; providing a second wafer, wherein the second wafer contains a micro-electrical-mechanical system (MEMS) device and a plurality of bonding pads, wherein the MEMS device includes at least one of;
actuators, mirrors, gyroscopes, or accelerometers; andbonding the first wafer and the second wafer together through a metal diffusion process and in a manner such that the bonding pads of the second wafer are bonded to the interconnect structure of the first wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of packaging, comprising:
-
providing a first wafer, wherein the first wafer contains a plurality of transistors and an interconnect structure having a plurality of metal layers; providing a second semiconductor wafer, wherein the second semiconductor wafer contains a through-silicon-via (TSV) and a bonding pad disposed on the TSV, wherein the TSV extends vertically through the second semiconductor wafer from a first surface of the second semiconductor wafer to a second surface of the second semiconductor wafer opposite the first surface; and bonding, through a metal diffusion process, the bonding pad of the second semiconductor wafer to a top-most metal layer of the interconnect structure of the first wafer. - View Dependent Claims (9, 10, 11, 12, 20)
-
-
13. A method of packaging, comprising:
-
providing a first semiconductor wafer and a second semiconductor wafer; forming a first bonding pad on the first wafer, the first bonding pad including a first bonding material; forming a second bonding pad on the second wafer, the second bonding pad including a second material different from the first material, one of the first and second materials being aluminum, and the other thereof being a titanium alloy; bonding the first and second wafers together through the first and second bonding pads; providing a third wafer; forming a third bonding pad on the first wafer, the third bonding pad including a third material; forming a fourth bonding pad on the third wafer, the fourth bonding pad having a fourth material different from the third material, one of the third and fourth materials being aluminum, and the other thereof being a titanium alloy; and after the bonding the first and second wafers, bonding the first and third wafers together through the third and fourth bonding pads. - View Dependent Claims (14, 15, 16, 17, 18, 19)
-
Specification