Display device and electronic device

• US 9,337,191 B2
• Filed: 11/04/2013
• Issued: 05/10/2016
• Est. Priority Date: 02/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi, Kimura, Hajime
• Primary Examiner(s): PATEL, PREMAL R
• Application Number:
  US14/070,700
• Publication Number:
  US 20140048810A1
• Time in Patent Office: 918 Days
• Field of Search: 345/92, 345/100, 345/211, 345/212
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10⁻¹⁸ A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

Claims

1. A circuit implementing a circuit diagram comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein, in the circuit diagram;

a first terminal of the first transistor is electrically connected to a first wiring;

a second terminal of the first transistor is electrically connected to a second wiring;

a first terminal of the second transistor is electrically connected to a third wiring;

a first terminal of the third transistor is electrically connected to a fourth wiring;

a first terminal of the fourth transistor is electrically connected to the third wiring;

a gate electrode of the first transistor is directly connected to a second terminal of the second transistor and a gate electrode of the fourth transistor;

a gate electrode of the second transistor is directly connected to a second terminal of the third transistor and a second terminal of the fourth transistor; and

a gate electrode of the third transistor is directly connected to the first terminal of the third transistor,

wherein a channel forming region of each of the first to fourth transistors includes an oxide semiconductor,

wherein the oxide semiconductor comprises indium, gallium and zinc, and

wherein an off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

2. The circuit according to claim 1, wherein carrier density of the channel forming region of each of the first to fourth transistors is less than 1×

10¹¹/cm³.

3. A display device including the circuit according to claim 1.

4. A semiconductor device comprising the circuit according to claim 1.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein;

a first terminal of the first transistor is electrically connected to a first wiring;

a second terminal of the first transistor is electrically connected to a second wiring;

a first terminal of the second transistor is electrically connected to a third wiring;

a first terminal of the third transistor is electrically connected to a fourth wiring;

a first terminal of the fourth transistor is electrically connected to the third wiring;

a gate electrode of the first transistor is directly connected to a second terminal of the second transistor and a gate electrode of the fourth transistor;

a gate electrode of the second transistor is directly connected to a second terminal of the third transistor and a second terminal of the fourth transistor; and

a gate electrode of the third transistor is directly connected to the first terminal of the third transistor,

wherein a channel forming region of each of the first to fourth transistors includes an oxide semiconductor,

wherein the oxide semiconductor comprises indium, gallium and zinc, and

wherein an off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

6. The semiconductor device according to claim 5, wherein carrier density of the channel forming region of each of the first to fourth transistors is less than 1×

10¹¹/cm³.

7. A display device including the semiconductor device according to claim 5.

8. A circuit implementing a circuit diagram comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein, in the circuit diagram;

a first terminal of the first transistor is electrically connected to a first wiring;

a second terminal of the first transistor is electrically connected to a second wiring;

a first terminal of the second transistor is electrically connected to a third wiring;

a first terminal of the third transistor is electrically connected to a fourth wiring;

a first terminal of the fourth transistor is electrically connected to the third wiring;

a gate electrode of the first transistor is directly connected to a second terminal of the second transistor and a gate electrode of the fourth transistor;

a gate electrode of the second transistor is directly connected to a second terminal of the third transistor and a second terminal of the fourth transistor;

a gate electrode of the third transistor is directly connected to the first terminal of the third transistor; and

the first wiring has a width which is smaller than a channel width of the first transistor.

9. The circuit according to claim 8, wherein the width is larger than a width of at least a part of the fourth wiring.

10. The circuit according to claim 8, wherein a channel forming region of each of the first to fourth transistors includes an oxide semiconductor.

11. The circuit according to claim 8 wherein off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

12. The circuit according to claim 8, wherein carrier density of a channel forming region of each of the first to fourth transistors is less than 1×

10¹¹/cm³.

13. A semiconductor device comprising the circuit according to claim 8.

14. A display device including the circuit according to claim 8.

15. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein;

a first terminal of the first transistor is electrically connected to a first wiring;

a second terminal of the first transistor is electrically connected to a second wiring;

a first terminal of the second transistor is electrically connected to a third wiring;

a first terminal of the third transistor is electrically connected to a fourth wiring;

a first terminal of the fourth transistor is electrically connected to the third wiring;

a gate electrode of the first transistor is directly connected to a second terminal of the second transistor and a gate electrode of the fourth transistor;

a gate electrode of the second transistor is directly connected to a second terminal of the third transistor and a second terminal of the fourth transistor;

a gate electrode of the third transistor is directly connected to the first terminal of the third transistor; and

the first wiring has a width which is smaller than a channel width of the first transistor.

16. The semiconductor device according to claim 15, wherein the width is larger than a width of at least a part of the fourth wiring.

17. The semiconductor device according to claim 15, wherein a channel forming region of each of the first to fourth transistors includes an oxide semiconductor.

18. The semiconductor device according to claim 15, wherein off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

19. The semiconductor device according to claim 15, wherein carrier density of a channel forming region of each of the first to fourth transistors is less than 1×

10¹¹/cm³.

20. A display device including the semiconductor device according to claim 15.