Semiconductor device and method of manufacturing semiconductor device

• US 9,337,256 B2
• Filed: 03/18/2013
• Issued: 05/10/2016
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Izumi, Naoki
• Primary Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US13/846,180
• Publication Number:
  US 20130214351A1
• Time in Patent Office: 1,149 Days
• Field of Search: 257/334
• US Class Current: 1/1
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A method of manufacturing a semiconductor device having a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field-Effect Transistor) and a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), including forming a semiconductor layer of a first conductivity type by epitaxy, forming a body region recess for forming a body region of the VDMOSFET on the semiconductor layer, and embedding a semiconductor material of a second conductivity type in the body region recess by epitaxy or CVD (Chemical Vapor Deposition).

Claims

1. A semiconductor device having a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field-Effect Transistor) and a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), comprising:

a semiconductor layer of a first conductivity type, the semiconductor layer having a body region recess formed thereon and recessed from a surface thereof in a first element forming region on which the VDMOSFET is formed;

a body region of a second conductivity type embedded in the body region recess; and

a well region of the second conductivity type formed in the surface of the semiconductor layer in a second element forming region on which the planar gate MOSFET is formed, wherein

each of the body region and the well region is an epitaxial layer, or a layer formed by chemical vapor deposition (CVD), that contains an impurity of the second conductivity type, and

the body region and the well region have the same impurity concentration profiles, with uniform impurity concentrations in the depth directions respectively.

2. The semiconductor device according to claim 1, further comprising:

a substrate of the first conductivity type on which the semiconductor layer is formed, an impurity concentration of the semiconductor layer being lower than an impurity concentration of the substrate,

a trench dug from the surface of the semiconductor layer, and penetrating the body region, and

a gate electrode embedded in the trench with a gate insulating film interposed between a surface of the trench and the gate electrode.

3. The semiconductor device according to claim 1, wherein a depth of the body region and a depth of the well region are equal to each other.

4. The semiconductor device according to claim 1, wherein the semiconductor layer has a well region recess formed thereon and recessed from the surface thereof in the second element forming region, the epitaxial layer or the CVD layer forming the well region being embedded in the well region recess.