Power switch acceleration scheme for fast wakeup

• US 9,337,825 B2
• Filed: 06/19/2014
• Issued: 05/10/2016
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Takayanagi, Toshinari, Suzuki, Shingo
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US14/308,886
• Publication Number:
  US 20140300407A1
• Time in Patent Office: 691 Days
• US Class Current: 1/1
• CPC Class Codes: H03K 17/0412 by measures taken in the control circuit
• CPC Class Codes: H03K 17/04206 in field-effect transistor switches
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 17/284 in field effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Claims

1. An integrated circuit comprising:

a first power gated circuit block coupled to receive power from a first virtual voltage node, the first virtual voltage node being exclusive to the first power gated circuit block;

a first plurality of power switches each coupled between the first virtual voltage node and a global voltage node that is non-exclusive to the first power gated circuit block;

a power control unit, the power control unit including a voltage detection circuit configured to generate a first indication when a voltage on the first virtual voltage node is less than a predetermined threshold voltage, and a second indication when the voltage on the first virtual voltage node is greater than the predetermined threshold, wherein the power control unit is configured to cause the first plurality of power switches to be sequentially activated at a first rate responsive to the voltage detection unit generating the first indication and at a second rate responsive to the voltage detection unit generating the second indication.

2. The integrated circuit as recited in claim 1, wherein the second rate is greater than the first rate.

3. The integrated circuit as recited in claim 1, further comprising a first plurality of delay elements coupled in a series configuration, wherein an output of each of the delay elements is coupled to a control terminal of a corresponding one of the power switches.

4. The integrated circuit as recited in claim 3, wherein the first plurality of delay elements is coupled to receive an enable signal from the power control unit, wherein all but a final one of the plurality of delay elements is coupled to provide the enable signal to an input of another delay element, and wherein a respective control terminal of each of the plurality of power switches is coupled to receive the enable signal from an output of a correspondingly coupled one of the first plurality of delay elements.

5. The integrated circuit as recited in claim 4, wherein each of the plurality of delay elements is coupled to receive a delay control signal from the power control unit, wherein the power control unit is configured to cause a change of delay provided by each of the plurality of delay elements by changing a state of the delay control signal.

6. The integrated circuit as recited in claim 1, further comprising:

a second power gated circuit block coupled to receive power from a second virtual voltage node, the second virtual voltage node being exclusive to the second power gated circuit block; and

a second plurality of power switches each coupled between the second virtual voltage node and the global voltage node;

wherein the power control unit is configured to cause the second plurality of power switches to be sequentially activated at the first rate responsive to a voltage on the first virtual voltage node being less than the predetermined threshold voltage and at a second rate greater than the first rate responsive to the voltage on the second virtual voltage node being greater than the predetermined threshold.

7. The integrated circuit as recited in claim 6, wherein the power control unit is configured to concurrently activate the first plurality of power switches and the second plurality of power switches.

8. A method of controlling power in an integrated circuit, comprising:

generating, by a power control unit of the integrated circuit, a first indication when a voltage detected on a first virtual voltage node is less than a predetermined threshold voltage;

generating, by the power control unit, a second indication when the voltage is greater than the predetermined threshold voltage;

sequentially activating, by the power control unit, a first plurality of power switches coupled between the first virtual voltage node of a first power gated circuit block and a global voltage node at a first response rate in response to the first indication is generated; and

sequentially activating, by the power control unit, the first plurality of power switches at a second rate in response to the second indication is generated.

9. The method as recited in claim 8, wherein the second rate is greater than the first rate.

10. The method as recited in claim 8, wherein the method further comprises an output of each of a first plurality of delay elements providing a signal to a control terminal of a respectively coupled one of the plurality of power switches.

11. The method as recited in claim 10, further comprising:

the first plurality of delay elements receiving an enable signal from the power control unit;

each of a subset of the first plurality of delay elements providing the enable signal to an input of another one of the plurality of delay elements; and

a respective control terminal of each of the plurality of power switches receiving the enable signal from its correspondingly coupled one of the first plurality of delay elements.

12. The method as recited in claim 11, further comprising:

receiving, at each of the first plurality of delay elements receiving a delay control signal from the power control unit;

changing an amount of delay provided by each of the plurality of delay elements responsive to the power control unit changing a state of the delay control signal.

13. The method as recited in claim 8, further comprising:

a second power gated circuit block receiving power from a second virtual voltage node, the second virtual voltage node being exclusive to the second power gated circuit block; and

the power control unit causing a second plurality of power switches to be sequentially activated at the first rate responsive to a voltage on the first virtual voltage node being less than the predetermined threshold voltage and at a second rate greater than the first rate responsive to the voltage on the second virtual voltage node being greater than the predetermined threshold, wherein each of the second plurality of power switches are coupled between the second virtual voltage node and the global voltage node.

14. The method as recited in claim 13, further comprising the power control unit causing the first plurality of power switches to be activated concurrently with activation of the second plurality of power switches.