Method and apparatus for aggregating input data streams

• US 9,338,100 B2
• Filed: 06/24/2013
• Issued: 05/10/2016
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks LLC (Broadcom, Inc.)
• Inventors: Wong, Yuen Fai, Lin, Yu-Mei, Grenier, Richard A.
• Primary Examiner(s): PATEL, CHANDRAHAS B
• Application Number:
  US13/925,564
• Publication Number:
  US 20140153389A1
• Time in Patent Office: 1,051 Days
• Field of Search: 370/468, 379/221.02
• US Class Current: 1/1
• CPC Class Codes: H04L 47/2433 Allocation of priorities to traffic types
• CPC Class Codes: H04L 47/6275 based on priority
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]

Abstract

A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

Claims

1. A system comprising:

a memory;

a plurality of input interfaces, wherein each input interface from the plurality of input interfaces is coupled to a corresponding processor and adapted to receive data packets from the corresponding processor, each data packet comprising at least one priority factor coded therein;

an output interface; and

a circuit coupled to the plurality of input interfaces and the output interface, the circuit adapted to;

receive data packets from the plurality of input interfaces; and

for each received data packet;

based on the at least one priority factor for the received data packet, determine a classification for the received data packet;

write packet data corresponding to the received data packet to the memory;

generate a packet descriptor for the received data packet, the packet descriptor containing a reference to the packet data stored in the memory; and

insert, based upon the classification, the generated packet descriptor in one of a plurality of queues, wherein the generated packet descriptor is inserted into a queue from the plurality of queues corresponding to the packet classification; and

the circuit further adapted to;

select a queue from the plurality of queues;

select a packet descriptor from the selected queue;

read, from the memory, packet data corresponding to the selected packet descriptor; and

send a data packet comprising the packet data read from the memory to the output interface.

2. The system of claim 1, wherein determining a classification is further based on decoding a header associated with the received data packet to extract the at least one priority factor.

3. The system of claim 1 further comprising an encoder coupled to the circuit and adapted to encode the data packet comprising the packet data read from the memory into an interface format.

4. The system of claim 1, wherein each received data packet is classified separately.

5. The system of claim 1, wherein the plurality of input interfaces and the output interface are adapted to provide logical interconnection between a Media Access Control sublayer (MAC) and a Physical layer (PHY).

6. The system of claim 1, wherein the circuit is further adapted to assert a flow control signal to at least one of the processors to temporarily pause the receipt of data packets.

7. A method comprising:

receiving, at a network device, data packets from a plurality of input interfaces, each input interface coupled to a corresponding processor and each received data packet comprising at least one priority factor coded therein;

for each received data packet;

determining a classification for the received data packet based on the at least one priority factor included with the received data packet;

writing packet data corresponding to the received data packet to a memory;

generating a packet descriptor for the received data packet, the packet descriptor containing a reference to the packet data stored in the memory; and

inserting, based upon the classification, the generated packet descriptor one of a plurality of queues, wherein the generated packet descriptor is inserted into a queue from the plurality of queues corresponding to the packet classification; and

selecting a queue from the plurality of queues;

selecting a packet descriptor from the selected queue;

reading, from the memory, packet data corresponding to the selected packet descriptor; and

sending a data packet comprising the packet data read from the memory to an output interface.

8. The method of claim 7, wherein the plurality of input interfaces and the output interface are adapted to provide logical interconnection between a Media Access Control sublayer (MAC) and a Physical layer (PHY).

9. The method of claim 7, wherein determining a classification is further based on decoding a header associated with the received data packet to extract the at least one priority factor.

10. The method of claim 7 further comprising encoding the data packet comprising the packet data read from the memory into an interface format.

11. The method of claim 7, wherein each received data packet is classified separately.

12. The method of claim 7, further comprising asserting a flow control signal to at least one of the processors to temporarily pause receipt of data packets.

13. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for:

receiving data packets from a plurality of input interfaces, each input interface coupled to a corresponding processor and each received data packet comprising at least one priority factor coded therein;

for each received data packet;

determining a classification for the received data packet based on the at least one priority factor included with the received data packet;

writing packet data corresponding to the received data packet to a memory;

generating a packet descriptor for the received data packet, the packet descriptor containing a reference to the packet data stored in the memory; and

inserting, based upon the classification, the generated packet descriptor in one of a plurality of queues, wherein the generated packet descriptor is inserted into a queue corresponding to the packet classification; and

selecting a queue from the plurality of queues;

selecting a packet descriptor from the selected queue;

reading, from the memory, packet data corresponding to the selected packet descriptor; and

sending a data packet comprising the packet data read from the memory to an output interface.

14. The non-transitory program storage device of claim 13, further comprising instructions executable by the machine for asserting a flow control signal to at least one of the processors to temporarily pause receipt of data packets.

15. The non-transitory program storage device of claim 13, wherein determining a classification is further based on decoding a header associated with the received data packet to extract the at least one priority factor.

16. The non-transitory program storage device of claim 13, further comprising instructions executable by the machine for encoding the data packet comprising the packet data read from the memory into an interface format.

17. The non-transitory program storage device of claim 13, wherein each received data packet is classified separately. data packets.