Column-based high dynamic range imaging systems

• US 9,338,372 B2
• Filed: 07/11/2013
• Issued: 05/10/2016
• Est. Priority Date: 09/19/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Cho, Kwangbo, Kim, Dongsoo
• Primary Examiner(s): Ye, Lin
• Assistant Examiner(s): HSU, AMY R
• Application Number:
  US13/940,055
• Publication Number:
  US 20140078365A1
• Time in Patent Office: 1,034 Days
• US Class Current: 1/1
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/583 with different integration times

Abstract

Electronic devices may have camera modules that include an image sensor and processing circuitry. An image sensor may include a pixel array having pixel rows and pixel columns. The image pixels in a pixel row may include long-integration pixels and short-integration pixels. Row control signal lines for each pixel row may include a row-select control line, a reset control line, and two transfer control lines or may include a row-select control line, two reset control lines, and a transfer control line. Row control circuitry may be used to operate the pixel array to capture a column-interleaved image with short-exposure pixel values and long-exposure pixel values interleaved in a column-based pattern. The column-interleaved image may be used to form an interpolated short-exposure image and an interpolated long-exposure image from which a column-based interleaved high-dynamic-range image is generated.

Claims

1. An image sensor, comprising:

an array of image pixels arranged in pixel rows and pixel columns;

a conductive column line coupled to each pixel column;

column readout circuitry coupled to the pixel columns through the conductive column lines; and

row control circuitry configured to operate the array of image pixels to capture a column-interleaved image with short-exposure pixel values and long-exposure pixel values that are interleaved in a column-based pattern, wherein the row control circuity comprises first and second reset lines coupled to each pixel row, wherein the first reset lines are coupled to a first set of pixels in each pixel row that capture the long-exposure pixel values and the second reset lines are coupled to a second set of pixels in each pixel row that capture the short-exposure pixel values, and wherein the row control circuitry is configured to provide reset control signals over the first and second reset lines to perform at least two resets of both the first and second sets of pixels between consecutive readouts of the long and short-exposure pixel values from the array of image pixels.

2. The image sensor defined in claim 1, further comprising:

a first transfer control line coupled to each pixel row; and

a second transfer control line coupled to each pixel row.

3. The image sensor defined in claim 2 wherein the first transfer control line that is coupled to each pixel row is coupled to a first set of image pixels in that pixel row for capturing the short-exposure pixel values and wherein the second transfer control line that is coupled to each pixel row is coupled to a second set of image pixels in that pixel row for capturing the long-exposure pixel values.

4. The image sensor defined in claim 3 wherein the first set of image pixels and the second set of image pixels are interleaved sets of image pixels.

5. The image sensor defined in claim 1 wherein the first set of image pixels and the second set of image pixels are interleaved sets of image pixels.

6. The image sensor defined in claim 5, further comprising:

a transfer control line coupled to the first set of image pixels and the second set of image pixels each pixel row.

7. The image sensor defined in claim 1, wherein at least one of the resets of both the first and second sets of pixels occur at a common time.

8. The image sensor defined in claim 7, wherein the first set of pixels is reset at an additional time which is after the common time.

9. The image sensor defined in claim 8, wherein the second set of pixels is reset after the additional time.

10. A system, comprising:

a central processing unit;

memory;

input-output circuitry;

an imaging device, wherein the imaging device comprises;

an array of image pixels arranged in pixel rows and pixel columns, wherein each pixel row includes short-integration pixels and long-integration pixels, wherein both the long-integration pixels and the short-integration pixels are reset at a common time, wherein the short-integration pixels are configured to transfer short-exposure pixel values to first charge storage regions on the short-integration pixels after a first exposure duration from the common time, wherein the long-integration pixels are configured to transfer long-exposure pixel values to second charge storage regions on the long-integration pixels after a second exposure duration from the common time, wherein the second exposure duration is greater than the first exposure duration,

a conductive column line coupled to each pixel column, and

column readout circuitry coupled to the pixel columns through the conductive column lines, wherein the column readout circuitry is configured to read out the long-exposure pixel values from the second charge storage regions and the short-exposure pixel values from the first charge storage regions at a common readout time; and

processing circuitry configured to generate a column-based interleaved high-dynamic-range image using a column-interleaved image captured by the array of image pixels.

11. The system defined in claim 10, wherein the imaging device further comprises row control circuitry configured to provide row control signals to each pixel row for capturing the column-interleaved image.

12. The image sensor of claim 10, wherein the short-exposure pixel values are transferred to the first charge storage regions before the long-exposure pixel values are transferred to the second charge storage regions.