Method and structure of monolithically integrated absolute pressure sensor

• US 9,340,414 B2
• Filed: 06/20/2014
• Issued: 05/17/2016
• Est. Priority Date: 07/07/2009
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yoneoka, Shingo, Flannery, Anthony F. Jr.
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/311,034
• Publication Number:
  US 20150315016A1
• Time in Patent Office: 697 Days
• Field of Search: 257/415
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: G01L 19/0084 to the outside of the housing other details about the housing see G01L19/14
• CPC Class Codes: G01L 19/143 Two part housings
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0045 Diaphragm associated with a buried cavity
• CPC Class Codes: G01L 9/0054 integral with a semiconducting diaphragm
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

An integrated pressure sensing device and method of fabrication thereof are disclosed. The method can include providing a substrate member having a surface region and forming a CMOS IC layer overlying the substrate and forming an oxide layer overlying the CMOS IC layer. A portion of the oxide layer can be removed to form a cavity region. A single crystalline silicon wafer can be bonded overlying the oxide surface region to seal the cavity region. The bonding process can include a fusion bonding or eutectic bonding process. The wafer can be thinned to a desired thickness and portions can be removed and filled with metal materials to form via structures. A pressure sensor device can be formed from the wafer, and can be co-fabricated with another sensor from the wafer. The pressure sensor and the other sensor can share a cavity pressure or have separate cavity pressures.

Claims

1. A method of fabricating an integrated pressure sensing device, the method comprising:

providing a substrate member having a surface region;

forming a CMOS IC layer overlying the surface region, the CMOS IC layer having a CMOS surface region;

forming an oxide layer overlying the CMOS surface region, the oxide layer having an oxide surface region;

removing at least a portion of the oxide layer to form at least a first cavity region;

bonding a single crystalline silicon wafer overlying the oxide surface region to seal the first cavity region;

thinning the single crystalline silicon wafer to a desired thickness;

removing at least a portion of the single crystalline silicon wafer to form at least one connection path;

depositing a metal material within the at least one connection path to form at least one via structure; and

removing at least a second portion of the single crystalline silicon wafer to expose a cavity path coupled to the first cavity region, the removed second portion of the single crystalline silicon being outside the sealed first cavity region.

2. The method of claim 1 wherein the bonding of the single crystalline silicon wafer includes a fusion bonding process or a eutectic bonding process.

3. The method of claim 2 wherein the bonding of the single crystalline silicon wafer is performed in a vacuum chamber forming a vacuum in the cavity region.

4. The method of claim 1 further comprising forming a thin film material overlying the single crystalline silicon wafer and covering an opening of the cavity path.

5. The method of claim 4 wherein the thin film material substantially seals the cavity path.

6. The method of claim 4 wherein the thin film material substantially seals at least a diffusion path of the integrated pressure sensing device.

7. The method of claim 4 wherein the thin film material comprises a PECVD silicon nitride or a SiO₂ material.

8. The method of claim 1 forming a thin film material overlaying the single crystalline silicon wafer, wherein the thin film material is formed via a deposition process with a pressure <

1000 Pa and a temperature <

350 degrees Celsius.

9. The method of claim 1 wherein the metal material comprises TiN and W materials.

10. The method of claim 1 wherein the CMOS surface region includes a top metal layer, and the first cavity region in the oxide layer is disposed over a first region of the top metal layer.

11. The method of claim 1 further comprising removing a second portion of the oxide layer to form a second cavity region and a path connecting the first cavity region and the second cavity region, the second cavity region being outside the sealed first cavity region.

12. The method of claim 11 wherein the removed second portion of the single crystalline silicon is above the second cavity region to form the cavity path.

13. A method of fabricating an integrated pressure sensing device, the method comprising:

providing a substrate member having a surface region;

forming a CMOS IC layer overlying the surface region, the CMOS IC layer having a CMOS surface region;

forming an oxide layer overlying the CMOS surface region, the oxide layer having an oxide surface region;

removing at least a portion of the oxide layer to form at least a cavity region;

bonding a single crystalline silicon wafer overlaying the oxide surface region to seal the cavity region;

thinning the single crystalline silicon wafer to a desired thickness;

removing at least a portion of the single crystalline silicon wafer to form at least one connection path;

depositing a metal material within the at least one connection path to form at least one via structure; and

removing at least a portion of the single crystalline silicon wafer to form a cavity path coupled to the cavity region;

the method-further comprising;

a first ion implantation process to form a heavily p-type doped region within a first portion of the single crystalline silicon wafer; and

a second ion implantation process to form a heavily p-type doped region within a second portion of the signal crystalline silicon wafer.

14. A method of fabricating an integrated pressure sensing device, the method comprising:

providing a substrate member having a surface region;

forming a CMOS IC layer overlying the surface region, the CMOS IC layer having a CMOS surface region, the CMOS region includes a top metal layer;

forming an oxide layer overlying the CMOS surface region, the oxide layer having an oxide surface region;

removing at least a portion of the oxide layer to form at least a first cavity region, the first cavity region in the oxide layer being disposed over a region of the top metal layer;

bonding a single crystalline silicon wafer overlying the oxide surface region to seal the first cavity region;

thinning the single crystalline silicon wafer to a desired thickness;

removing at least a portion of the single crystalline silicon wafer to form at least one connection path;

depositing a metal material within the at least one connection path to form at least one via structure; and

removing a second portion of the oxide layer to form a second cavity region and a path connecting the first cavity region and the second cavity region, the second cavity region being outside the sealed first cavity region.

15. The method of claim 14 further comprising removing a second portion of the single crystalline silicon wafer to over the second cavity region to form a cavity path coupled to the first cavity region, the removed second portion of the single crystalline silicon being outside the sealed first cavity region.

16. The method of claim 14 further comprising forming a MEMS (micro-electrical-mechanical-system) sensor over the second cavity region.

17. The method of claim 16 further comprising forming a cap structure overlying another sensor, the cap structure having a cap cavity region.

18. The method of claim 17 wherein the forming of the cap structure includes a eutectic bonding process to substantially seal the cavity path.

19. The method of claim 17 wherein the forming of the MEMS sensor from the second portion forming a cavity path, the cap cavity region being connected to the cavity region via the cavity path.

20. The method of claim 17 wherein the cap cavity region is separated from the cavity region.

21. The method of claim 17 wherein the cap structure comprises at least one isolation input channel having an input port, the isolation input channel being configured to protect the pressure sensor from mechanical damage.

22. The method of claim 16 wherein the MEMS sensor comprises one or more of an accelerometer, a gyro sensor, a resonator, a magnetic field sensor, a pressure sensor, or a reference pressure sensor.