Nonvolatile logic array and power domain segmentation in processing device

• US 9,342,259 B2
• Filed: 02/19/2013
• Issued: 05/17/2016
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bartling, Steven Craig, Khanna, Sudhanshu
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Hicks, Austin
• Application Number:
  US13/770,498
• Publication Number:
  US 20140075218A1
• Time in Patent Office: 1,183 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 3/3562 of the master-slave type
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

Claims

1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements;

a processing core;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a first power domain configured to supply power to switched logic elements of the computing device apparatus;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the computing device apparatus associated with the processing core and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the computing device apparatus associated with the processing core;

wherein operation of the first set of at least one of the plurality of non-volatile logic element arrays is independent of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

a second power domain configured to supply power to logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays;

a third power domain configured to supply power for the plurality of non-volatile logic element arrays;

wherein individual ones of the first power domain, the second power domain, and the third power domain are configured to be powered down or up independently of other ones of the first power domain, the second power domain, and the third power domain;

wherein the third power domain is configured to be powered down during regular operation of the computing device apparatus.

2. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements;

a processing core;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a first power domain configured to supply power to switched logic elements of the computing device apparatus;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the computing device apparatus associated with the processing core and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the computing device apparatus associated with the processing core;

wherein operation of the first set of at least one of the plurality of non-volatile logic element arrays is independent of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

a second power domain configured to supply power to logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays;

a third power domain configured to supply power for the plurality of non-volatile logic element arrays;

wherein individual ones of the first power domain, the second power domain, and the third power domain are configured to be powered down or up independently of other ones of the first power domain, the second power domain, and the third power domain;

wherein the first power domain is configured to be powered down during a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements.

3. A method comprising:

operating a processing device with a processing core using a plurality of volatile storage elements;

storing data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the processing device associated with the processing core and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the processing device associated with the processing core;

wherein the method further comprises controlling operation of the first set of at least one of the plurality of non-volatile logic element arrays independently of operation of the second set of at least one of the plurality of non-volatile logic element arrays

in response to receiving a signal indicating the disruption of system power, entering a system backup mode and powering up the third power domain;

powering a primary logic circuit portion of individual ones of the plurality of volatile storage elements by a first power domain;

powering logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays by a second power domain;

powering the plurality of non-volatile logic element arrays by a third power domain;

powering up or down individual ones of the first power domain, the second power domain, and the third power domain independently of other ones of the first power domain, the second power domain, and the third power domain;

in response to the at least one non-volatile logic controller determining that the system backup mode is complete, entering a sleep mode and powering down the first power domain, the second power domain, and third power domain;

in response to receiving a signal indicating a restoration of power while in a sleep mode, entering a system restore mode and powering on the second power domain and the third power domain and maintaining the first power domain as powered down;

in response to the at least one non-volatile logic controller determining that the system restore mode is complete, entering a regular operation mode, powering up the first power domain and the second power domain, and powering down the third power domain.

4. A method comprising:

operating a processing device with a processing core using a plurality of volatile storage elements;

storing data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the processing device associated with the processing core and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the processing device associated with the processing core;

wherein the method further comprises controlling operation of the first set of at least one of the plurality of non-volatile logic element arrays independently of operation of the second set of at least one of the plurality of non-volatile logic element arrays

in response to receiving a signal indicating the disruption of system power, entering a system backup mode and powering up the third power domain;

powering a primary logic circuit portion of individual ones of the plurality of volatile storage elements by a first power domain;

powering logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays by a second power domain;

powering the plurality of non-volatile logic element arrays by a third power domain;

powering up or down individual ones of the first power domain, the second power domain, and the third power domain independently of other ones of the first power domain, the second power domain, and the third power domain;

powering non-volatile logic element arrays associated with the first function by a first portion of the third power domain;

powering non-volatile logic element arrays associated with the second function by a second portion of the third power domain;

individually powering up or down the first portion and the second portion of the third power domain independently of other portions of the first power domain.

5. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements comprising retention flip flops;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a first power domain configured to supply power to switched logic elements of the computing device apparatus and configured to be powered down during a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first domain comprising a first portion configured to supply power to switched logic elements associated with a first function and a second portion configured to supply power to switched logic elements associated with a second function;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with the first function of the computing device apparatus and a second set of at least one of the plurality of non-volatile logic element arrays is associated with the second function of the computing device apparatus;

wherein operation of the first set of at least one of the plurality of non-volatile logic element arrays is independent of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

wherein the first portion and the second portion of the first power domain are individually configured to be powered up or down independently of other portions of the first power domain;

a second power domain configured to supply power to a slave stage of individual ones of the retention flip flops;

a third power domain configured to supply power for the plurality of non-volatile logic element arrays and configured to be powered down during regular operation of the computing device apparatus;

a fourth power domain configured to supply power to real time clocks and wake-up interrupt logic;

integral power gates configured to be controlled to power down the individual ones of the first power domain, the second power domain, and the third power domain;

wherein individual ones of the first power domain, the second power domain, and the third power domain are configured to be powered down or up independently of other ones of the first power domain, the second power domain, and the third power domain;

wherein the third power domain is divided into a first portion configured to supply power to non-volatile logic element arrays associated with the first function and a second portion configured to supply power to non-volatile logic element arrays associated with the second function;

wherein the first portion and the second portion of the third power domain are individually configured to be powered up or down independently of other portions of the third power domain.

6. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a first power domain configured to supply power to switched logic elements of the computing device apparatus;

a second power domain configured to supply power to logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays;

a third power domain configured to supply power for the plurality of non-volatile logic element arrays;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the computing device apparatus and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the computing device apparatus;

wherein operation of the first set of at least one of the plurality of non-volatile logic element arrays is independent of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

wherein individual ones of the first power domain, the second power domain, and the third power domain are configured to be powered down or up independently of other ones of the first power domain, the second power domain, and the third power domain;

wherein the third power domain is configured to be powered down during regular operation of the computing device apparatus.

7. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a first power domain configured to supply power to switched logic elements of the computing device apparatus;

a second power domain configured to supply power to logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays;

a third power domain configured to supply power for the plurality of non-volatile logic element arrays;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the computing device apparatus and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the computing device apparatus;

wherein operation of the first set of at least one of the plurality of non-volatile logic element arrays is independent of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

wherein individual ones of the first power domain, the second power domain, and the third power domain are configured to be powered down or up independently of other ones of the first power domain, the second power domain, and the third power domain;

wherein the first power domain is configured to be powered down during a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements.

8. A method comprising:

operating a processing device using a plurality of volatile storage elements;

storing data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the processing device and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the processing device;

wherein the method further comprises;

controlling operation of the first set of at least one of the plurality of non-volatile logic element arrays independently of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

powering a primary logic circuit portion of individual ones of the plurality of volatile storage elements by a first power domain;

powering logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays by a second power domain;

powering the plurality of non-volatile logic element arrays by a third power domain;

powering up or down individual ones of the first power domain, the second power domain, and the third power domain independently of other ones of the first power domain, the second power domain, and the third power domain;

in response to receiving a signal indicating the disruption of system power, entering a system backup mode and powering up the third power domain;

in response to the at least one non-volatile logic controller determining that the system backup mode is complete, entering a sleep mode and powering down the first power domain, the second power domain, and third power domain;

in response to receiving a signal indicating a restoration of power while in a sleep mode, entering a system restore mode and powering on the second power domain and the third power domain and maintaining the first power domain as powered down;

in response to the at least one non-volatile logic controller determining that the system restore mode is complete, entering a regular operation mode, powering up the first power domain and the second power domain, and powering down the third power domain elements.

9. A method comprising:

operating a processing device using a plurality of volatile storage elements;

storing data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays;

wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the processing device and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the processing device;

wherein the method further comprises;

controlling operation of the first set of at least one of the plurality of non-volatile logic element arrays independently of operation of the second set of at least one of the plurality of non-volatile logic element arrays;

powering a primary logic circuit portion of individual ones of the plurality of volatile storage elements by a first power domain;

powering logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays by a second power domain;

powering the plurality of non-volatile logic element arrays by a third power domain;

powering up or down individual ones of the first power domain, the second power domain, and the third power domain independently of other ones of the first power domain, the second power domain, and the third power domain;

powering non-volatile logic element arrays associated with the first function by a first portion of the third power domain;

powering non-volatile logic element arrays associated with the second function by a second portion of the third power domain;

individually powering up or down the first portion and the second portion of the third power domain independently of other portions of the first power domain.