De-duplication in flash memory module

• US 9,343,153 B2
• Filed: 07/14/2015
• Issued: 05/17/2016
• Est. Priority Date: 10/26/2010
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamura, Atsushi, Ogawa, Junji
• Primary Examiner(s): Parikh, Kalpit
• Application Number:
  US14/798,888
• Publication Number:
  US 20150317097A1
• Time in Patent Office: 308 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0641 De-duplication techniques
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.

Claims

1. A non-volatile semiconductor memory module comprising:

a plurality of non-volatile semiconductor memory chips including a plurality of physical pages, wherein each physical page of the plurality of physical pages is a unit for writing/reading data; and

a memory controller configured to manage;

a first data set and a first guarantee code set, wherein the first data set includes a plurality of first user data and the first guarantee code set includes a plurality of first guarantee codes, wherein each of the plurality of first guarantee codes is associated with each of the plurality of first user data, and

a second data set and a second guarantee code set, wherein the second data set includes a plurality of second user data and the second guarantee code set includes a plurality of second guarantee codes, wherein each of the plurality of second guarantee codes is associated with each of the plurality of first user data,

wherein if the first data set and the second data set are the same data set, the memory controller compresses the same data set into a compressed data and stores the compressed data, the first guarantee code set and the second guarantee code set into a first physical page of the plurality of physical pages.

2. The non-volatile semiconductor memory module of claim 1, wherein:

each of the plurality of first guarantee codes and each of the plurality of second guarantee codes includes;

a bit error correction code part calculated from the user data associated with the guarantee code, and

a target address part, wherein the target address part is an address of the user data associated with the guarantee code.

3. The non-volatile semiconductor memory module of claim 1, wherein each of the plurality of first guarantee codes and each of the plurality of second guarantee codes are different.

4. The non-volatile semiconductor memory module of claim 1, wherein a location of each of the plurality of first guarantee codes and each of the plurality of second guarantee codes in the first physical page is stored as an offset value relative to a top address of the first physical page.

5. The non-volatile semiconductor memory module of claim 4, wherein the offset value is stored in a logical/physical address conversion table.

6. The non-volatile semiconductor memory module of claim 1, wherein the memory controller is further configured to perform read processing, including:

acquiring a logical page address to be read,

acquiring target logical/physical address information from a logical/physical address conversion table,

determining whether the acquired logical page was subject to de-duplication processing,

if the acquired logical page was not subject to de-duplication processing, then acquiring a physical page address corresponding to the logical page,

if the acquired logical page was subject to de-duplication processing, then;

acquiring a physical page data address where a data part of the logical page is stored,

acquiring a physical page code address where guarantee codes of the logical page are stored, and

acquiring a physical page code offset address to identify a physical location of the guarantee codes within the physical page, and

reading data stored in a physical page based on the physical page address.

7. The non-volatile semiconductor memory module of claim 1, wherein the non-volatile semiconductor memory is a flash memory.

8. A storage apparatus comprising:

a storage controller; and

a plurality of non-volatile semiconductor memory modules, each of the plurality of non-volatile semiconductor memory modules including;

a plurality of non-volatile semiconductor memory chips including a plurality of physical pages, wherein each physical page of the plurality of physical pages is a unit for writing/reading data, and

a memory controller configured to manage;

a first data set and a first guarantee code set, wherein the first data set includes a plurality of first user data and the first guarantee code set includes a plurality of first guarantee codes, wherein each of the plurality of first guarantee codes is associated with each of the plurality of first user data, and

a second data set and a second guarantee code set, wherein the second data set includes a plurality of second user data and the second guarantee code set includes a plurality of second guarantee codes, wherein each of the plurality of second guarantee codes is associated with each of the plurality of first user data,

wherein if the first data set and the second data set are the same data set, the memory controller compresses the same data set into a compressed data and stores the compressed data, the first guarantee code set and the second guarantee code set into a first physical page of the plurality of physical pages.

9. The storage apparatus of claim 8, wherein:

each of the plurality of first guarantee codes and each of the plurality of second guarantee codes includes;

a bit error correction code part calculated from the user data associated with the guarantee code, and

a target address part, wherein the target address part is an address of the user data associated with the guarantee code.

10. The storage apparatus of claim 8, wherein each of the plurality of first guarantee codes and each of the plurality of second guarantee codes are different.

11. The storage apparatus of claim 8, wherein a location of each of the plurality of first guarantee codes and each of the plurality of second guarantee codes in the first physical page is stored as an offset value relative to a top address of the first physical page.

12. The storage apparatus of claim 11, wherein the offset value is stored in a logical/physical address conversion table.

13. The storage apparatus of claim 8, wherein the memory controller is further configured to perform read processing, including:

acquiring a logical page address to be read,

acquiring target logical/physical address information from a logical/physical address conversion table,

determining whether the acquired logical page was subject to de-duplication processing,

if the acquired logical page was not subject to de-duplication processing, then acquiring a physical page address corresponding to the logical page,

if the acquired logical page was subject to de-duplication processing, then;

acquiring a physical page data address where a data part of the logical page is stored,

acquiring a physical page code address where guarantee codes of the logical page are stored, and

acquiring a physical page code offset address to identify a physical location of the guarantee codes within the physical page, and

reading data stored in a physical page based on the physical page address.

14. The storage apparatus of claim 8, wherein at least one of the plurality of non-volatile semiconductor memory modules is a flash memory module.