Nonvolatile memory device and driving method thereof

• US 9,343,154 B2
• Filed: 08/06/2015
• Issued: 05/17/2016
• Est. Priority Date: 11/08/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Changhyun
• Primary Examiner(s): Le, Vu
• Application Number:
  US14/819,428
• Publication Number:
  US 20150340093A1
• Time in Patent Office: 285 Days
• Field of Search: 365/185.17, 365/185.02, 365/185.11, 365/185.24
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.

Claims

1. A nonvolatile memory device, comprising:

a plurality of memory strings including a first memory cell string that includes at least two serially-connected selection transistors and a plurality of serially-connected nonvolatile memory cells, the at least two serially-connected selection transistors being connected between a first bit-line and the plurality of serially-connected nonvolatile memory cells, the plurality of serially-connected nonvolatile memory cells being stacked in a direction that is perpendicular to a substrate, the at least two serially-connected selection transistors including a first string selection transistor and a second string selection transistor; and

a control logic configured to perform a program operation for setting a threshold voltage of at least one of the first string selection transistor and the second string selection transistor,

wherein the first string selection transistor is connected to the first bit-line and has a first threshold voltage, and

the second string selection transistor is disposed between the first string selection transistor and the plurality of serially-connected nonvolatile memory cells, the second string selection transistor having a second threshold voltage.

2. The nonvolatile memory device of claim 1, wherein the control logic is configured to verify the at least one of the first string selection transistor and the second string selection transistor using a verification voltage.

3. The nonvolatile memory device of claim 2, wherein the at least one of the first string selection transistor and the second string selection transistor has the same structure as the plurality of serially-connected nonvolatile memory cells, and

the first memory cell string includes a ground selection transistor which is an enhancement type transistor that is not programmable.

4. The nonvolatile memory device of claim 1, wherein the at least one of the first string selection transistor and the second string selection transistor includes the second string selection transistor.

5. The nonvolatile memory device of claim 1, wherein the control logic is configured to perform the program operation for setting the first threshold voltage and the second threshold voltage.

6. The nonvolatile memory device of claim 5, wherein the control logic is configured to verify the first string selection transistor and the second string selection transistor.

7. The nonvolatile memory device of claim 4, wherein the control logic is configured to apply a program voltage to the second string selection transistor and to apply a program-pass voltage to the first string selection transistor while the program voltage is applied to the first string selection transistor, the program-pass voltage being higher than a power supply voltage.

8. The nonvolatile memory device of claim 5, wherein the control logic is configured to verify the first string selection transistor using a first verification voltage and the second string selection transistor using a second verification voltage, and

the first verification voltage is different from the second verification voltage.

9. The nonvolatile memory device of claim 8, wherein the first verification voltage is higher than the second verification voltage.

10. The nonvolatile memory device of claim 2, wherein the control logic is configured to apply a program bit-line voltage to the first bit-line to program the at least one of the first string selection transistor and the second string selection transistor, and configured to apply a program-inhibit voltage to the first bit-line to program-inhibit the at least one of the first string selection transistor and the second string selection transistor.

11. The nonvolatile memory device of claim 10, wherein the control logic is configured to apply the program bit-line voltage to the first bit-line and to apply the program-inhibit voltage to the first bit-line, based on a result of verifying the at least one of the first string selection transistor and the second string selection transistor.

12. A nonvolatile memory device, comprising:

a plurality of memory strings including a first memory cell string and a second memory cell string, each of the plurality of memory strings including a plurality of serially-connected nonvolatile memory cells stacked in a direction that is perpendicular to a substrate, each of the first memory cell string and the second memory cell string being connected to a first bit-line, at least one memory cell of each of the plurality of memory strings being connected to a first word-line, the first memory cell string including a first string selection transistor connected to the first bit-line and a second string selection transistor disposed between the first string selection transistor and the plurality of serially-connected nonvolatile memory cells of the first memory cell string; and

a control logic configured to perform a program operation and a program-inhibit operation for setting a threshold voltage of at least one of the first string selection transistor and the second string selection transistor by applying a program pulse to the at least one of the first string selection transistor and the second string selection transistor,

wherein the first string selection transistor and the second string selection transistor have the same structure as the plurality of serially-connected nonvolatile memory cells, and

the program operation and the program-inhibit operation are controlled by varying a bit-line bias applied to the first bit-line during the applying the program pulse to the at least one of the first string selection transistor and the second string selection transistor.

13. The nonvolatile memory device of claim 12, wherein the control logic is configured to perform the program operation for setting the threshold voltage of the second string selection transistor, and to perform a program-verify operation to the second string selection transistor.

14. The nonvolatile memory device of claim 13, wherein the threshold voltage of the first string selection transistor is higher than the threshold voltage of the second string selection transistor.

15. The nonvolatile memory device of claim 12, wherein

the control logic is configured to perform the program operation for setting the threshold voltage of both the first string selection transistor and the second string selection transistor,

the control logic is configured to perform a program-verify operation to the first string selection transistor using a first verification voltage and the second string selection transistor using a second verification voltage,

the first verification voltage is different from the second verification voltage.

16. The nonvolatile memory device of claim 13, wherein the bit-line bias for the program-inhibit operation is higher than the bit-line bias for the program operation, and

the bit-line bias is varied based on a result of the program-verify operation performed to the second string selection transistor using the first verification voltage.

17. The nonvolatile memory device of claim 16, wherein a program-pass voltage is applied to the first word-line during the program operation.

18. A nonvolatile memory device, comprising:

a plurality of memory strings including a first memory cell string and a second memory cell string, each of the plurality of memory strings including a plurality of serially-connected nonvolatile memory cells stacked in a direction that is perpendicular to a substrate, each of the first memory cell string and the second memory cell string being connected to a first bit-line, at least one memory cell of each of the plurality of memory strings being connected to a first word-line, the first memory cell string including a first string selection transistor connected to the first bit-line and a second string selection transistor disposed between the first string selection transistor and the plurality of serially-connected nonvolatile memory cells of the first memory cell string; and

a control logic configured to perform a program operation and a program-inhibit operation for setting a threshold voltage of the first string selection transistor by applying a program pulse to the first string selection transistor, the control logic being configured to perform a program-verify operation to the first string selection transistor,

wherein the first string selection transistor has the same structure as the plurality of serially-connected nonvolatile memory cells,

the first memory cell string includes a ground selection transistor which is an enhancement type transistor that is not programmable,

the program operation and the program-inhibit operation are controlled by varying a bit-line bias applied to the first bit-line during the applying the program pulse to the first string selection transistor, and

the bit-line bias is varied based on a result of the program-verify operation.

19. The nonvolatile memory device of claim 18, wherein the bit-line bias for the program-inhibit operation is higher than the bit-line bias for the program operation.

20. The nonvolatile memory device of claim 19, wherein a program-pass voltage is applied to the first word-line during the program operation.