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Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability

  • US 9,343,182 B2
  • Filed: 07/10/2013
  • Issued: 05/17/2016
  • Est. Priority Date: 07/10/2013
  • Status: Active Grant
First Claim
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1. A method of measuring the delay from wordline input to bitline output of a static random access memory (SRAM) cell, said method comprising:

  • providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell;

    generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input;

    generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input;

    measuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell; and

    monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes.

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