Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability

• US 9,343,182 B2
• Filed: 07/10/2013
• Issued: 05/17/2016
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jungmann, Noam, Wagner, Israel A.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/939,008
• Publication Number:
  US 20150015274A1
• Time in Patent Office: 1,042 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Claims

1. A method of measuring the delay from wordline input to bitline output of a static random access memory (SRAM) cell, said method comprising:

providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell;

generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input;

generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input;

measuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell; and

monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes.

2. The method according to claim 1, further comprising precharging the bitline to an appropriate charge level in response to the falling edge of said wordline.

3. The method according to claim 1, wherein if cell data does change, generating a second output indicating existence of a stability problem.

4. The method according to claim 1, further comprising guaranteeing an initial state of said delay stage circuit whereby an incorrect state is corrected in a subsequent memory cycle.

5. The method according to claim 1, further comprising locating cell under test within a mini-array so as to emulate realistic capacitance and resistance conditions on said bitline.

6. A direct memory ring oscillator (DMRO) circuit for measuring the wordline to bitline delay of a static random access memory (SRAM) cell, comprising:

a plurality of delay stage circuits, each delay stage circuit comprising;

an SRAM cell;

circuitry operative to generate a falling edge of the output of a delay stage circuit in response to the rising edge of the wordline, to generate a rising edge of the output of said delay stage circuit in response to the falling edge of the wordline, to measure the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell, and to monitor stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes;

wherein measuring the frequency of said DMRO corresponds to the wordline to bitline delay of said SRAM cell.

7. The circuit according to claim 6, further comprising circuitry operative to precharge the bitline to an appropriate charge level in response to the falling edge of said wordline.

8. The circuit according to claim 6, further comprising circuitry operative to generate a second output indicating a stability problem in response to detecting a change in said predefined value.

9. The circuit according to claim 6, further comprising circuitry operative to guarantee an initial state of said delay stage circuit whereby an incorrect state is corrected in a subsequent memory cycle.

10. The circuit according to claim 6, further comprising placing the cell under test in a mini-array of SRAM cells so as to emulate realistic conditions as much as possible.

11. A method of measuring the delay and stability of a static random access memory (SRAM) cell, said method comprising:

incorporating the delay from a wordline input to a bitline output of said SRAM cell into delay stages of a ring oscillator;

measuring the frequency of oscillation of said ring oscillator, wherein said frequency corresponds to said wordline to bitline delay; and

monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes.

12. The method according to claim 11, further comprising generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input, and generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input.

13. The method according to claim 11, further comprising precharging the bitline to an appropriate charge level in response to the falling edge of said wordline.

14. The method according to claim 11, wherein if cell data does change, generating a second output indicating existence of a random read instability problem.

15. The method according to claim 11, further comprising guaranteeing an initial state of said delay stage circuit whereby an incorrect state is corrected in a subsequent memory cycle.

16. The method according to claim 11, further comprising locating the cell under test within a mini-array so as to emulate realistic conditions of operation.

17. The method according to claim 11, further comprising wherein drop in frequency indicates read instability in said SRAM cell.