Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability
First Claim
1. A method of measuring the delay from wordline input to bitline output of a static random access memory (SRAM) cell, said method comprising:
- providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell;
generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input;
generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input;
measuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell; and
monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes.
1 Assignment
0 Petitions
Accused Products
Abstract
A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.
-
Citations
17 Claims
-
1. A method of measuring the delay from wordline input to bitline output of a static random access memory (SRAM) cell, said method comprising:
-
providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell; generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input; generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input; measuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell; and monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A direct memory ring oscillator (DMRO) circuit for measuring the wordline to bitline delay of a static random access memory (SRAM) cell, comprising:
a plurality of delay stage circuits, each delay stage circuit comprising; an SRAM cell; circuitry operative to generate a falling edge of the output of a delay stage circuit in response to the rising edge of the wordline, to generate a rising edge of the output of said delay stage circuit in response to the falling edge of the wordline, to measure the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell, and to monitor stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes; wherein measuring the frequency of said DMRO corresponds to the wordline to bitline delay of said SRAM cell. - View Dependent Claims (7, 8, 9, 10)
-
11. A method of measuring the delay and stability of a static random access memory (SRAM) cell, said method comprising:
-
incorporating the delay from a wordline input to a bitline output of said SRAM cell into delay stages of a ring oscillator; measuring the frequency of oscillation of said ring oscillator, wherein said frequency corresponds to said wordline to bitline delay; and monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes. - View Dependent Claims (12, 13, 14, 15, 16, 17)
-
Specification