Memory device retention mode based on error information

• US 9,343,183 B2
• Filed: 08/20/2014
• Issued: 05/17/2016
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Guo, Ziyu, Kong, Xiangming, Zhang, Shayan
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US14/463,674
• Publication Number:
  US 20150106671A1
• Time in Patent Office: 636 Days
• Field of Search: 714/721, 714/718, 714/746
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.

Claims

1. A controller for a memory device, comprising:

a power control section to control power to a memory element of the memory device in an operation mode and in a retention mode;

a monitoring section for receiving and monitoring error information indicative of an error in the memory device; and

a storage section for storing a retention parameter, wherein,

the power control section causes an operation voltage to be applied to the memory element in the operation mode, and causes a time-varying voltage to be applied to the memory element in the retention mode,

the time-varying voltage changes between a first retention voltage and a second retention voltage, the second retention voltage being less than the first retention voltage, and the first retention voltage being less than the operation voltage,

the power control section controls the second retention voltage based on the retention parameter, and

the retention parameter is set based on the error information.

2. The controller of claim 1, wherein the error information is based on an error correction code.

3. The controller of claim 1, wherein the error information is determined based on a result of reading the memory in the operation mode.

4. The controller of claim 1, wherein the memory element is a reference memory element selected from a plurality of memory elements that form the memory device, the reference memory element selected based on a determination that the reference memory element is more susceptible to errors due to low voltage than other memory elements of the plurality of memory elements.

5. The controller of claim 1, wherein the memory element is selected from a plurality of memory elements based on a detection of an error in the memory element during the operation mode.

6. The controller of claim 5, wherein the retention parameter is set based on a number of detected errors in the memory element exceeding a predetermined threshold.

7. The controller of claim 1, wherein in the retention mode the power control section causes first and second applied voltages to be applied to the memory element, and wherein the retention parameter is used to determine at least one of,

the value of the second applied voltage, and

a timing for applying one or both of the first and second applied voltages in the retention mode,

such that in the retention mode the voltage across the memory element varies between the first retention voltage and the second retention voltage.

8. The controller of claim 1, wherein the retention parameter is selected from a plurality of retention parameters based on a user-controlled setting.

9. The controller of claim 1, further comprising:

a frequency controller, arranged to receive a user-controlled setting and the retention parameter, for controlling periods of time that a first applied voltage and a second applied voltage are supplied to the memory device,

wherein the frequency controller includes,

a selection section that selects, based on the user controlled setting, one of a clock based on a default value of the retention parameter and a clock based on an adjusted value of the retention parameter, and

a synch section that synchronizes the clock selected by the selection section with a system clock.

10. A device, comprising:

a memory device; and

a controller coupled to the memory device, the controller comprising;

a power control section to control power to a memory element of the memory device in an operation mode and in a retention mode;

a monitoring section for receiving and monitoring error information indicative of an error in the memory device; and

a storage section for storing a retention parameter, wherein,

the power control section causes an operation voltage to be applied to the memory element in the operation mode, and a time-varying voltage to be applied to the memory element in the retention mode,

the power control section causes the time-varying voltage to change between a first retention voltage and a second retention voltage, the second retention voltage being less than the first retention voltage, and the first retention voltage being less than the operation voltage,

the power control section controls the second retention voltage based on the retention parameter, which is set based on the error information.

11. A method of controlling power to memory elements of a memory device, comprising:

providing an operation voltage to the memory device in an operation mode;

providing a time-varying voltage to the memory device in a retention mode;

changing the time-varying voltage, based on a retention parameter, between a first retention voltage value and a second retention voltage value, the second retention voltage value being less than the first retention voltage value, and the first retention voltage being less than a value of the operation voltage;

receiving error information indicative of an error in a memory element of the memory device; and

setting the retention parameter based on the error information.

12. The method of claim 11, wherein the error information is based on an error correction code.

13. The method of claim 11, wherein the error information is based on a result of reading the memory in the operation mode.

14. The method claim 11, wherein the memory element is a reference memory element selected from the memory elements based on a determination that the reference memory element is more susceptible to errors due to low voltage than other ones of the memory elements.

15. The method of claim 11, wherein the memory element is selected based on a detection of an error in the memory element during the operation mode.

16. The method of claim 15, wherein the retention parameter is set based on a number of detected errors in the memory element exceeding a predetermined threshold.

17. The method of claim 11, wherein the retention parameter is changed when the received error information indicates at least one of an occurrence of an error in a pre-selected reference memory element, and at least two occurrences of an error in a memory element other than the pre-selected reference memory element.

18. The method of claim 11, wherein in the retention mode the first and second retention voltages are applied to the memory element, and wherein the retention parameter determines at least one of the value of the second applied voltage, and a timing for applying one or both of the first and second retention voltages such that the voltage across the memory element varies between the first retention voltage and the second retention voltage.

19. The method of claim 11, wherein the retention parameter is selected from a plurality of retention parameters based on a user-controlled setting.

20. The method of claim 11, further comprising:

setting the retention parameter when the error information indicates that detected errors satisfy a predetermined condition, the predetermined condition being one of;

a) no errors in the memory device for a first interval;

b) only single-bit errors in a second interval;

c) no errors in a predetermined reference memory element; and

d) a logical combination of two or more of a to c.