Semiconductor storage device

• US 9,343,186 B2
• Filed: 09/10/2014
• Issued: 05/17/2016
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Komai, Hiromitsu
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US14/482,697
• Publication Number:
  US 20150254010A1
• Time in Patent Office: 615 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.

Claims

1. A semiconductor storage device comprising:

a cell array;

a redundant array provided logically separated from the cell array, the redundant array comprising a column area replaceable with a defective column in the cell array;

a cache memory comprising a storing area of data read from or written in the cell array by one access, the cache memory allowing interleave access to a plurality of divided areas to which the area is logically divided;

a defective column storage to store a column address of a defective column in the cell array;

a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage; and

a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area that corresponds to the defective column, at the generation timing of the clock accessing the divided page buffer area, to generate a clock accessing the redundant array that has stored data of the defective column.

2. The device of claim 1 further comprising:

a plurality of first latches to latch data at shifted timings with the clocks generated by the clock generator; and

a plurality of second latches to latch the data latched by the first latches or data which should be latched by the first latches at a common timing,

wherein, in data writing to the cell array, the data latched by the second latches are stored in column areas of the divided areas so that data latched by each second latch is stored in one column area of each divided area, and

in data reading from the cell array, the data stored in the column areas of the divided areas are latched by the second latches at a common timing.

3. The device of claim 2, wherein

the cache memory has two or more divided redundant areas storing data in place of data of two or more defective columns in the cell array, and

when the defective column determination module determines that a column address to be accessed matches the column address stored in the defective column storage, instead of generating a clock accessing a divided area corresponding to a column address of the defective column, the clock generator generates a clock accessing any one of the two or more divided redundant areas at a generation timing of the clock accessing the divided area corresponding to the column address of the defective column.

4. The device of claim 1, wherein the clock generator generates a same number of clocks for each period of the interleave access irrespective of whether there is a defective column in the cell array.

5. The device of claim 1, wherein the clock generator generates a plurality of clocks at a predetermined timing for each period of the interleave access irrespective of whether there is a defective column in the cell array.

6. The device of claim 5 further comprising signal terminals monitoring clocks of the second latches.

7. The device of claim 1, wherein the cell array and the redundant array provided logically separated from each other are arranged in a row direction, and row decoders are arranged on both sides of arranged cell and redundant arrays.

8. The device of claim 1, wherein

the cell array comprises a user column area storing data in each column so as to be associated with a column address specified by a user and an ECC column area storing error correction data in each column,

the redundant array comprises a redundant column area with which data of a defective column in the user column area is replaceable.

9. The device of claim 1, wherein

the cell array and the redundant array are logically divided into an m number of divided all areas and an n (n being an integer equal to or smaller than m) number of divided redundant array areas, respectively, as associated with the divided areas, and

a maximum n number of defective columns are replaced with redundant columns in respective redundant array areas within one interleave period.

10. The device of claim 1, wherein the cell array is a NAND flash memory cell array.

11. The device of claim 1, wherein

the cell array is divided into a plurality of blocks aligned in a column direction, each block being a unit of erase, and

the cache memory is accessed per bit line that connects the blocks in the column direction.