Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems

• US 9,343,369 B2
• Filed: 05/19/2014
• Issued: 05/17/2016
• Est. Priority Date: 05/19/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Du, Yang, Arabi, Karim
• Primary Examiner(s): HENRY, CALEB E
• Application Number:
  US14/280,731
• Publication Number:
  US 20150333056A1
• Time in Patent Office: 729 Days
• Field of Search: 257/546, 257/E29.019, 257/E21.505, 257/E21.514, 257/E25.013, 257/E27.026
• US Class Current: 1/1
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/08147 the bonding area connecting to a bonding area disposed in a recess of the surface of the body
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80357 being flush with the surface
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/83125 Bonding areas on the body
• CPC Class Codes: H01L 2224/83895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

Claims

1. A three dimensional (3D) integrated circuit (IC) (3DIC), comprising:

a first tier comprising;

a first holding substrate;

a first transistor positioned above the first holding substrate; and

a first interconnection metal layer positioned above the first transistor, wherein the first interconnection metal layer comprises a first metal bonding pad; and

a second tier comprising;

a second interconnection metal layer comprising a second metal bonding pad bonded to the first metal bonding pad;

a second transistor positioned above the second interconnection metal layer, the second transistor comprising a second gate and a second gate back surface; and

a second back gate bias positioned above and proximate the second gate back surface.

2. The 3DIC of claim 1, further comprising a second back metal layer positioned above the second back gate bias.

3. The 3DIC of claim 2, further comprising a via coupling the second back metal layer to the second interconnection metal layer.

4. The 3DIC of claim 2, wherein the second back metal layer comprises a second back metal bonding pad.

5. The 3DIC of claim 1, wherein the first holding substrate comprises a silicon holding substrate.

6. The 3DIC of claim 1, wherein the first holding substrate comprises a glass holding substrate.

7. The 3DIC of claim 1, further comprising a first back gate bias positioned proximate a gate of the first transistor.

13. The 3DIC of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.

8. A three dimensional (3D) integrated circuit (IC) (3DIC) comprising:

a first tier comprising;

a first holding substrate;

a first interconnection metal layer positioned above the first holding substrate;

a first transistor positioned above the first interconnection metal layer;

a first metal back layer positioned above the first transistor, wherein the first metal back layer comprises a first metal bonding pad; and

a via coupling the first metal back layer to the first interconnection metal layer; and

a second tier comprising;

a second interconnection metal layer comprising a second metal bonding pad bonded to the first metal bonding pad;

a second transistor positioned above the second interconnection metal layer, the second transistor comprising a second gate and a second gate back surface; and

a second back gate bias positioned above and proximate the second gate back surface.

9. The 3DIC of claim 8, further comprising a second back metal layer positioned above the second back gate bias.

10. The 3DIC of claim 9, further comprising a via coupling the second back metal layer to the second interconnection metal layer.

11. The 3DIC of claim 9, wherein the second back metal layer comprises a second back metal bonding pad.

12. The 3DIC of claim 8, further comprising a first back gate bias positioned proximate a gate of the first transistor.

14. The 3DIC of claim 8 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.