TSV formation processes using TSV-last approach

• US 9,343,390 B2
• Filed: 11/30/2012
• Issued: 05/17/2016
• Est. Priority Date: 07/12/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Chen, Lin, Yung-Chi, Yang, Ku-Feng
• Primary Examiner(s): Vu, David
• Application Number:
  US13/691,178
• Publication Number:
  US 20130093042A1
• Time in Patent Office: 1,264 Days
• Field of Search: 257/737, 257/784, 257/E21.499, 257/E23.011, 257/690, 257/691, 257/692, 257/693, 438/55, 438/106, 438/107, 438/113, 438/124, 438/125, 438/126, 438/127
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]

Abstract

A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Claims

1. A circuit structure comprising:

a semiconductor substrate;

a shallow trench isolation (STI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate;

a metal pad extending from a top surface of the STI region into the STI region, wherein the metal pad is encircled by the STI region, with an edge of the metal pad being in contact with an inner edge of the STI region to form an interface; and

a through-substrate via (TSV) extending from a back surface of the semiconductor substrate to contact a first portion of a bottom surface of the metal pad, with a second portion of the bottom surface of the metal pad extending beyond edges of the TSV.

2. The circuit structure of claim 1 further comprising:

an inter-layer dielectric (ILD) over the STI region, wherein the metal pad further extends into the ILD.

3. The circuit structure of claim 1, wherein the interface is lower than the top surface of the semiconductor substrate.

4. The circuit structure of claim 1, wherein a bottom surface of the metal pad is between the top surface and a bottom surface of the STI region, and wherein the TSV penetrates through a lower portion of the STI region to contact the metal pad.

5. The circuit structure of claim 1, wherein a top surface of the STI region is lower than a top surface of the metal pad.

6. The circuit structure of claim 1, wherein the interface extends from the top surface of the semiconductor substrate into the semiconductor substrate.

7. The circuit structure of claim 1, wherein the bottom surface of the STI region is at an intermediate level between the top surface and the back surface of the semiconductor substrate.

8. The circuit structure of claim 1, wherein the STI region has substantially vertical sidewalls extending to an intermediate level between the top surface and the back surface of the semiconductor substrate.

9. The circuit structure of claim 8, wherein the STI region extends beyond a sidewall of the metal pad outwardly for a first thickness, and the STI region extends deeper than the metal pad by a second thickness, and the first thickness is greater than the second thickness.

10. A circuit structure comprising:

a semiconductor substrate;

a shallow trench isolation (STI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate;

a metal pad extending from a level higher than a top surface of the STI region into a center portion the STI region, with an outer portion of the STI region forming a ring encircling the metal pad, wherein the outer portion comprises an inner edge in physical contact an edge of the metal pad to form an interface, and the interface forms a full ring; and

a through-substrate via (TSV) extending from a back surface of the semiconductor substrate to contact a bottom surface of the metal pad.

11. The circuit structure of claim 10 further comprising:

an inter-layer dielectric (ILD) over the STI region, wherein the metal pad further extends into the ILD, and wherein edges of a portion of the metal pad in the ILD are substantially aligned to respective edges of a portion of the metal pad in the STI region.

12. The circuit structure of claim 11, wherein the interface extends from the top surface of the semiconductor substrate into the semiconductor substrate.

13. The circuit structure of claim 10, wherein the STI region and the metal pad have circular-shaped edges.

14. The circuit structure of claim 10 further comprising:

an additional STI region, wherein both the STI region and the additional STI region extend from the top surface of the semiconductor substrate to stop at a same intermediate level between the top surface and the back surface of the semiconductor substrate; and

a transistor comprising a source/drain region having a sidewall contacting a sidewall of the additional STI region.

15. A circuit structure comprising:

a semiconductor substrate;

a first shallow trench isolation (STI) region and a second STI region extending from a top surface of the semiconductor substrate into the semiconductor substrate, with bottom surfaces of both the first STI region and the second STI region at a same intermediate level between a top surface and a bottom surface of the semiconductor substrate;

a transistor comprising a source/drain region having a sidewall contacting a sidewall of the second STI region;

a metal pad extending from a level higher than a top surface of the first STI region into a center portion the first STI region, with an outer portion of the first STI region forming a ring encircling the metal pad; and

a through-substrate via (TSV) extending from a back surface of the semiconductor substrate to contact a bottom surface of the metal pad.

16. The circuit structure of claim 15, wherein the outer portion comprises an inner edge in physical contact an edge of the metal pad to form an interface, and the interface forms a full ring.

17. The circuit structure of claim 15, wherein the first STI region and the second STI region are formed of a same dielectric material.