Dual damascene gap filling process

• US 9,343,400 B2
• Filed: 03/13/2013
• Issued: 05/17/2016
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Hsiang-Huan, Shue, Shau-Lin
• Primary Examiner(s): Zhang, Yuanda
• Assistant Examiner(s): Maruf, Sheikh
• Application Number:
  US13/802,100
• Publication Number:
  US 20140264908A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257/774, 257/751, 257/E21.584, 257/E21.577, 257/E21.175, 438/653, 438/294, 438/597
• US Class Current: 1/1
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/532 characterised by the materials
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric layer having a plurality of first openings. A first conductive layer is formed in the plurality of first openings. A patterned mask layer is formed over portions of the first conductive layer outside the plurality of first openings, the patterned mask layer having a plurality of second openings, wherein at least a subset of the second openings are disposed over the first openings. A second conductive layer is filled in the plurality of second openings. The patterned mask layer is removed to leave behind the conductive layer structures on the substrate. The substrate is heated to form a self-forming barrier layer on the top and sidewalls of the conductive layer structures.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming an etching stop layer over a substrate;

forming a patterned dielectric layer over the etching stop layer, the etching stop layer disposed between the patterned dielectric layer and the substrate, the patterned dielectric layer having a plurality of first openings;

forming a first conductive layer in the plurality of first openings;

forming a mask layer over first portions of the patterned dielectric layer disposed outside the plurality of first openings, the mask layer having a plurality of second openings, wherein at least a subset of the second openings are disposed over the first openings;

filling a second conductive layer in the plurality of second openings, the second conductive layer defining conductive layer structures shaped by the second openings, the conductive layer structures disposed laterally adjacent to the mask layer;

removing the mask layer laterally adjacent to the conductive layer structures to leave behind the first portions of the patterned dielectric layer and the conductive layer structures on the substrate; and

after the removing, annealing the conductive layer structures to form a self-forming barrier layer on a top and sidewalls of the conductive layer structures.

2. The method of claim 1, further comprising:

prior to forming a first conductive layer in the first openings, depositing a diffusion barrier layer on a bottom and sidewalls of the dielectric layer in the plurality of first openings.

3. The method of claim 1, wherein the mask layer comprises a patterned photoresist layer.

4. The method of claim 1, wherein the forming a mask layer is carried out in a manner such that at least some of the second openings are wider than the respective first openings disposed therebelow.

5. The method of claim 1, further comprising after the annealing, depositing a dielectric material layer onto a surface of the substrate in areas between the conductive layer structures and planarizing the substrate to remove excess dielectric material layer to expose the top of the conductive layer structures.

6. The method of claim 1, wherein the second conductive layer includes a material selected from the group consisting of:

CuMn, CuCr, CuV, CuTi, and CuNb.

7. The method of claim 1, wherein the filling the second conductive layer in the second openings is carried out by depositing a copper material in an electroless copper bottom-up fill process.

8. The method of claim 1, wherein the self-forming barrier layer includes a material selected from the group consisting of MnOx, CrOx, VOx, TiOx, NbOx, and combinations thereof.

9. The method of claim 1, wherein the self-forming barrier layer includes a material selected from the group consisting of TiN, TaN, TiSiN, TaSiN, SiN, SiCN, CoWP, CoWB, CoReP, NiWP, NiWB, NiReP, W, and combinations thereof.

20. The method of claim 1, wherein a portion of the self-forming barrier layer is disposed over the patterned dielectric layer.

10. A method of forming a metallization layer, comprising:

forming a plurality of first metal layer structures in a dielectric layer on a semiconductor substrate;

prior to forming the plurality of first metal layer structures, depositing a diffusion barrier layer in the dielectric layer that conforms to a bottom and side surfaces of the first metal layer structures;

forming a patterned photoresist layer over a first surface of the dielectric layer, the patterned photoresist layer having a plurality of openings that define second metal layer structures that are to be formed, wherein at least a subset of the openings are disposed over the plurality of first metal layer structures;

filling a conductive layer in the plurality of openings, the conductive layer disposed laterally adjacent to the patterned photo resist layer;

removing the patterned photoresist layer laterally adjacent to the conductive layer from the substrate to expose the first surface of the dielectric layer and to leave second metal layer structures on the dielectric layer and respective first metal layer structures; and

annealing the substrate to form a self-forming barrier layer on a top and sidewalls of the second metal layer structures.

11. The method of claim 10, further comprising depositing a dielectric material layer onto a surface of the substrate in areas between the second metal layer structures and planarizing the substrate to remove excess conductive material from the second metal layer structures and dielectric material layer to expose a top of the second metal layer structures.

12. The method of claim 10, wherein the conductive layer includes a material selected from the group consisting of:

CuMn, CuCr, CuV, CuTi, and CuNb.

13. The method of claim 10, wherein the filling the conductive layer in the plurality of openings is carried out by depositing a copper material in an electroless copper bottom-up fill process.

14. The method of claim 10, wherein the self-forming barrier layer includes a material selected from the group consisting of MnOx, CrOx, VOx, TiOx, NbOx, and combinations thereof.

15. The method of claim 10, wherein the self-forming barrier layer includes a material selected from the group consisting of TiN, TaN, TiSiN, TaSiN, SiN, SiCN, CoWP, CoWB, CoReP, NiWP, NiWB, NiReP, W, and combinations thereof.

16. A method of forming semiconductor device, comprising:

forming an etching stop layer between a patterned dielectric layer and a semiconductor substrate;

disposing a plurality of first metal layer structures within the patterned dielectric layer on the semiconductor substrate;

disposing over each of the plurality of first metal layer structures a second metal layer structure, the second metal layer structures disposed laterally adjacent to a mask layer, the mask layer overlying first portions of the patterned dielectric layer;

removing the mask layer laterally adjacent to the second metal layer structures to expose a top surface and sidewalls of each second metal layer structure while leaving behind the first portions of the patterned dielectric layer;

disposing a barrier layer on the exposed top surface and sidewalls of each second metal layer structure; and

disposing a dielectric material layer onto a surface of the patterned dielectric layer and in areas between the second metal layer structures.

17. The method of claim 16, wherein at least some of the second metal layer structures are formed to be wider than the respective first metal layer structures disposed below.

18. The method of claim 16, further comprising conformally forming a diffusion barrier layer in the patterned dielectric layer conformed to a bottom and side surfaces of the first metal layer structures.

19. The method of claim 16, wherein the barrier layer includes a material selected from the group consisting of MnOx, CrOx, VOx, TiOx, NbOx, and combinations thereof.