Use of device assembly for a generalization of three-dimensional metal interconnect technologies

• US 9,343,426 B1
• Filed: 01/07/2013
• Issued: 05/17/2016
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Parvarandeh, Pirooz
• Primary Examiner(s): Wagner, Jenny L
• Assistant Examiner(s): BOYLE, ABBIGALE A
• Application Number:
  US13/735,821
• Time in Patent Office: 1,226 Days
• Field of Search: 257/704
• US Class Current: 1/1
• CPC Class Codes: H01L 21/673 using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders holders for supporting a complete device in operation H01L23/32
• CPC Class Codes: H01L 2221/68313 Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/95101 in a liquid medium
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 2224/95143 Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15155 : the shape of the recess being other than a cuboid
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.

Claims

1. A method of assembly comprising:

assembling a plurality of singulated first die onto a carrier substrate;

fabricating a plurality of second die on a first side of a second substrate;

assembling a plurality of singulated third die onto a second side of the second substrate;

stacking the second substrate and the carrier substrate such that the plurality of second die are facing the plurality of first die, wherein the first side of the second substrate and a first side of the carrier substrate face each other such that active circuitry of the plurality of first die faces active circuitry of the plurality of second die;

bonding the plurality of first die directly to the plurality of second die such that at least one second die is operatively bonded to a respective first die to furnish an electrical interconnect between the at least one second die and the respective first die and third die;

forming vias through the second substrate to establish electrical interconnects between the first, second, and third die such that the at least one second die and the respective first die are both electrically connected to a respective third die, wherein at least one of the vias is formed through the at least one second die;

removing the carrier substrate, thereby leaving the plurality of first die exposed; and

;

after removing the carrier substrate, adding a cap structure over the plurality of first die and coupling the cap structure to the second substrate such that a surface opposite an active circuit portion of each of the plurality of first die is facing the cap structure, wherein the cap structure includes a plurality of cavities, each cavity aligned with a corresponding one first die and having a shape and a size that matches the corresponding one first die.

2. The method of claim 1, wherein each of the plurality of first die has a metalized back surface.

3. The method of claim 1, further comprising applying an insulating layer over the plurality of bonded first die and the second substrate.

4. The method of claim 1, further comprising:

cutting through the cap structure and the second substrate to form at least one singulated die stack including the at least one second die, the respective first die, and the respective third die.