Integrated circuit for high-voltage device protection

• US 9,343,465 B2
• Filed: 08/29/2014
• Issued: 05/17/2016
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yao, Chih-Wen Albert, Chu, Chen-Liang, Liu, Ruey-Hsin, Lei, Ming-Ta
• Primary Examiner(s): WHALEN, DANIEL B
• Application Number:
  US14/472,496
• Publication Number:
  US 20160064394A1
• Time in Patent Office: 627 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor

Abstract

Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate including a memory region and a logic region;

a memory device arranged over the memory region, the memory device including a floating gate arranged over a channel region of the memory device; and

a logic device arranged over the logic region, the logic device including a gate arranged over a channel region of the logic device, wherein the gate comprises a first polysilicon layer arranged below a second polysilicon layer, wherein the first polysilicon layer has a first average grain size and the second polysilicon layer has a second average grain size, wherein the first average grain size is different than the second average grain size.

2. The integrated circuit of claim 1, wherein the first and second polysilicon layers are structurally distinct in that the first and second polysilicon layers abut one another at a seam, which makes the first and second polysilicon layers distinct.

3. The integrated circuit of claim 1, further comprising:

a tunneling dielectric configured to electrically isolate the floating gate from the channel region of the memory device;

a control gate formed over at least a portion of the floating gate, wherein the control gate is configured to promote tunneling of electrons between the channel region of the memory device and the floating gate through the tunneling dielectric; and

an insulating layer configured to electrically isolate the control gate from the floating gate.

4. The integrated circuit of claim 3, wherein the insulating layer comprises one or more oxide layers, one or more nitride layers, or a combination thereof.

5. The integrated circuit of claim 3,

wherein the first polysilicon layer has a first thickness;

wherein the second polysilicon layer has a second thickness that is less than the first thickness; and

wherein the control gate is made of polysilicon and has a third thickness that is greater than the first thickness.

6. The integrated circuit of claim 3, further comprising an oxide layer disposed on an upper surface of the floating gate below the insulating layer.

7. The integrated circuit of claim 6, further comprising a second memory device that shares a common source region with the memory device.

8. The integrated circuit of claim 1, further comprising:

a source region and a drain region that are laterally separated by the channel region of the memory device, which resides below the floating gate of the memory device; and

an erase gate disposed over the source region of the memory device, wherein the erase gate is configured to promote tunneling of electrons between the floating gate and the erase gate.

9. The integrated circuit of claim 1, wherein the logic device further comprises a pair of sidewall spacers extending continuously along sidewalls of the first and second polysilicon layers and from an upper surface of the second polysilicon layer to an upper surface of the semiconductor substrate.

10. The integrated circuit of claim 9, wherein the memory device further comprises:

a control gate comprising a lower control gate portion arranged along a first sidewall of the floating gate and an upper control gate portion which extends over an upper surface of the floating gate and which is continuous with the lower control gate portion; and

an insulating layer configured to electrically isolate the control gate from the floating gate.

11. The integrated circuit of claim 10, further comprising:

a floating gate spacer arranged along a second sidewall of the floating gate, the second sidewall being opposite the first sidewall of the floating gate; and

first and second control gate spacers arranged on opposite sidewalls of the control gate, wherein the first control gate spacer is disposed along a sidewall of the lower control gate portion and the second control gate spacer is disposed along a sidewall of the upper control gate portion.

12. An integrated circuit, comprising:

a semiconductor substrate including a memory region and a logic region;

a logic device arranged over the logic region, the logic device including a gate that is separated from a channel region of the logic device by a gate dielectric, wherein the gate comprises a first polysilicon layer arranged below a second polysilicon layer, wherein the first polysilicon layer has a first average grain size and the second polysilicon layer has a second average grain size, wherein the first average grain size is different than the second average grain size; and

a memory device arranged over the memory region, the memory device including;

a floating gate that is separated from a channel region of the memory device by a tunneling dielectric, which is thinner than the gate dielectric;

a control gate formed over at least a portion of the floating gate; and

an insulating layer configured to electrically isolate the control gate from the floating gate.

13. The integrated circuit of claim 12, wherein the first polysilicon layer, the second polysilicon layer, and the control gate have different thicknesses.

14. The integrated circuit of claim 12, wherein the first polysilicon layer and the floating gate have about a same thickness.

15. The integrated circuit of claim 12, wherein the logic device further comprises a pair of sidewall spacers extending continuously along sidewalls of the first and second polysilicon layers and from an upper surface of the second polysilicon layer to an upper surface of the semiconductor substrate.

16. The integrated circuit of claim 15, wherein the control gate comprises a lower control gate portion arranged along a first sidewall of the floating gate and an upper control gate portion which extends over an upper surface of the floating gate and which is continuous with the lower control gate portion.

17. The integrated circuit of claim 16, further comprising:

a floating gate spacer arranged along a second sidewall of the floating gate, the second sidewall being opposite the first sidewall of the floating gate; and

first and second control gate spacers arranged on opposite sidewalls of the control gate, wherein the first control gate spacer is disposed along a sidewall of the lower control gate portion and the second control gate spacer is disposed along a sidewall of the upper control gate portion.

18. An integrated circuit, comprising:

a semiconductor substrate including a memory region and a logic region;

a memory device arranged over the memory region, the memory device including;

a floating polysilicon gate arranged over a channel region of the memory device;

a control gate comprising a lower control gate portion arranged along a first sidewall of the floating polysilicon gate and an upper control gate portion which extends over an upper surface of the floating polysilicon gate and which is continuous with the lower control gate portion; and

an insulating layer configured to electrically isolate the control gate from the floating polysilicon gate;

a logic device arranged over the logic region, the logic device including;

a gate arranged over a channel region of the logic device, wherein the gate comprises a first polysilicon layer arranged below a second polysilicon layer, wherein the first and second polysilicon layers are in direct electrical contact with one another and are structurally distinct from one another, wherein the floating polysilicon gate and the first polysilicon layer have the same thickness as one another; and

a pair of sidewall spacers extending continuously along sidewalls of the first and second polysilicon layers and from an upper surface of the second polysilicon layer to an upper surface of the semiconductor substrate; and

a floating gate spacer arranged along a second sidewall of the floating polysilicon gate, the second sidewall opposite the first sidewall of the floating polysilicon gate; and

first and second control gate spacers arranged on opposite sidewalls of the control gate, wherein the first control gate spacer is disposed along a sidewall of the lower control gate portion and the second control gate spacer is disposed along a sidewall of the upper control gate portion.

19. The integrated circuit of claim 18, further comprising:

an oxide layer disposed on the upper surface of the floating gate and disposed between the floating gate and the insulating layer.

20. The integrated circuit of claim 18, wherein the first and second polysilicon layers are structurally distinct in that the first and second polysilicon layers abut one another at a seam, which makes the first and second polysilicon layers distinct.