Method of fabricating GaN high voltage HFET with passivation plus gate dielectric multilayer structure

• US 9,343,541 B2
• Filed: 01/14/2014
• Issued: 05/17/2016
• Est. Priority Date: 12/01/2011
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Ramdani, Jamal, Liu, Linlin, Edwards, John Paul
• Primary Examiner(s): Rodela, Eduardo A
• Assistant Examiner(s): Roland, Christopher M
• Application Number:
  US14/154,355
• Publication Number:
  US 20140124789A1
• Time in Patent Office: 854 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02249 formation by combined oxidation and nitridation performed simultaneously
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02315 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.

Claims

1. A method of forming a passivation plus gate dielectric multilayer structure for a hetero-junction field-effect transistor (HFET) device comprising:

(a) exposing, in a reaction chamber, a top surface of a nitride-based semiconductor wafer to a first source that forms a film of material on the top surface;

(b) performing, within the reaction chamber, a first plasma strike that reacts with the film to form a nitride-based passivation layer on the top surface;

(c) exposing, in the reaction chamber, the nitride-based semiconductor wafer to a second source that results in a reaction of a material on a surface of the nitride-based passivation layer;

(d) performing, within the reaction chamber, a second plasma strike that reacts with the material to form an oxy-nitride layer directly on the nitride-based passivation layer, the nitride-based passivation layer and the oxy-nitride layer comprising a gate dielectric of the HFET device.

2. The method of claim 1 wherein the first source comprises aluminum (Al), the first plasma strike comprises nitrogen (N) and the nitride-based passivation layer comprises AlN.

3. The method of claim 1 wherein the first source comprises silicon (Si), the first plasma strike comprises nitrogen (N) and the nitride-based passivation layer comprises SiN.

4. The method of claim 1 wherein the first source comprises a tri-methyl aluminum (TMA) source.

5. The method of claim 1 further comprising repeating steps (a) and (b) until the nitride-based passivation layer is formed to a first thickness.

6. The method of claim 5 further comprising repeating steps (c) and (d) until the oxy-nitride layer is formed to a second thickness, the second thickness being greater than the first thickness.

7. The method of claim 6 wherein the second thickness is in a range of about 10-25 nm thick.

8. The method of claim 5 wherein the first thickness is in a range of about 2-10 nm thick.

9. The method of claim 1 further comprising, before step (a), loading the nitride-based semiconductor wafer into a reaction chamber, the nitride-based semiconductor wafer not being removed from the reaction chamber until completion of steps (a)-(d).

10. The method of claim 1 further comprises forming a silicon nitride layer atop the oxy-nitride layer;

wherein the oxy-nitride layer is formed with a graded nitrogen composition that varies from a highest atomic percentage at or near the silicon nitride layer to a lowest atomic percentage at or near the oxy-nitride layer.

11. The method of claim 1 wherein the top surface of the nitride-based semiconductor wafer comprises an AlGaN layer.

12. The method of claim 11 wherein the AlGaN layer is formed atop a GaN layer, a two dimensional electron gas channel (2-DEG) being formed at an interface between the AlGaN layer and the GaN layer.

13. The method of claim 1 wherein the reaction chamber comprises an Atomic Layer Deposition (ALD) reaction chamber.

14. The method of claim 1 wherein the film of material comprises aluminum.

15. The method of claim 1 wherein the film of material comprises silicon.