Frequency divider, clock generating apparatus, and method capable of calibrating frequency drift of oscillator

• US 9,344,065 B2
• Filed: 10/07/2013
• Issued: 05/17/2016
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Ying, Yu-Ming, Liu, Shiue-Shin
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US14/048,035
• Publication Number:
  US 20140111257A1
• Time in Patent Office: 953 Days
• Field of Search: 327/156, 327/158, 327/161
• US Class Current: 1/1
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.

Claims

1. A clock generating apparatus, comprising:

an oscillator, for generating a reference clock signal; and

a frequency synthesizer, coupled to the oscillator, for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus;

wherein the frequency synthesizer is utilized for calibrating a frequency of the target clock signal by adjusting/compensating the frequency division factor according to process variation information.

2. The clock generating apparatus of claim 1, wherein the frequency synthesizer comprises:

a divider having a division factor, for generating a first clock signal by using the division factor according to the reference clock signal; and

a phase-locked loop, coupled to the divider, for receiving the first clock signal and synthesizing the target clock signal based on the first clock signal;

wherein the divider adjusts/compensates the division factor to adjust/compensate a frequency of the first clock signal, so as to adjust/compensate the frequency of the target clock signal.

3. The clock generating apparatus of claim 1, wherein the frequency synthesizer comprises:

a phase-locked loop having a divider on a feedback path of the phase-locked loop, for synthesizing the target clock signal according to the reference clock signal;

wherein the divider includes a division factor which can be adjusted by the phase-locked loop; and

, the phase-locked loop adjusts/compensates the division factor so as to adjust/compensate the frequency of the target clock signal and outputting the target clock signal as the output of the clock generating apparatus.

4. The clock generating apparatus of claim 1, wherein the frequency synthesizer is utilized for calibrating the frequency of the target clock signal by adjusting/compensating the frequency division factor further according to temperature variation information;

the process variation information includes a set of process parameters corresponding to different process variations, and the temperature variation information includes a set of temperature parameters corresponding to different temperature variations; and

, the frequency synthesizer selects a process parameter from the set of process parameters or a temperature parameter from the set of temperature parameters by referring to a current fabrication process or a current temperature, and utilizes the selected process parameter or the selected temperature parameter to adjust/compensate the frequency division factor so as to calibrate the frequency of the target clock signal.

5. The clock generating apparatus of claim 4, further comprising:

a table recording the set of process parameters or the set of temperature parameters.

6. The clock generating apparatus of claim 1, being installed on a single integrated circuit chip.

7. The clock generating apparatus of claim 1, wherein the process variation information is obtained at a chip probing flow or a final test flow.

8. The clock generating apparatus of claim 1, wherein the frequency synthesizer is arranged to adjust/compensate the frequency division factor further according to temperature variation information which is collected by a temperature sensor external to the clock generating apparatus.

9. A method used for a clock generating apparatus, comprising:

providing an oscillator for generating a reference clock signal;

synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and the step of synthesizing the target clock signal comprises;

calibrating a frequency of the target clock signal by adjusting/compensating the frequency division factor according to process variation information; and

outputting the target clock signal as an output of the clock generating apparatus.

10. The method of claim 9, wherein the step of synthesizing the target clock signal comprises:

generating a first clock signal by dividing the reference clock signal using a division factor;

using a phase-locked loop to receive the first clock signal and synthesize the target clock signal based on the first clock signal;

wherein the step of generating the first clock signal comprises;

adjusting/compensating the division factor to adjust/compensate a frequency of the first clock signal, so as to adjust/compensate the frequency of the target clock signal.

11. The method of claim 9, wherein the step of synthesizing the target clock signal comprises:

using a phase-locked loop having a divider on a feedback path of the phase-locked loop to synthesize the target clock signal according to the reference clock signal;

wherein the step of synthesizing the target clock signal comprises;

adjusting/compensating a division factor of the divider so as to adjust/compensate the frequency of the target clock signal.

12. The method of claim 9, wherein the frequency division factor is compensated/adjusted further according to temperature variation information;

the process variation information includes a set of process parameters corresponding to different process variations, and the temperature variation information includes a set of temperature parameters corresponding to different temperature variations, and the step of synthesizing the target clock signal comprises;

selecting a process parameter from the set of process parameters or a temperature parameter from the set of temperature parameters by referring to a current fabrication process or a current temperature; and

utilizing the selected process parameter or the selected temperature parameter to adjust/compensate the frequency division factor so as to calibrate the frequency of the target clock signal.

13. The method of claim 9, further comprising:

obtaining the process variation information at a chip probing flow or a final test flow.

14. The method of claim 9, wherein the step of calibrating the frequency of the target clock signal by adjusting/compensating the frequency division factor comprises:

adjusting/compensating the frequency division factor further according to temperature variation information which is collected by a temperature sensor external to the clock generating apparatus.