Digital correction of spurious tones caused by a phase detector of a hybrid analog-digital delta-sigma modulator based fractional-N phase locked loop

• US 9,344,271 B1
• Filed: 03/25/2015
• Issued: 05/17/2016
• Est. Priority Date: 03/25/2014
• Status: Active Grant

• Current Assignee: Microsemi Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Original Assignee: Microsemi Storage Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Inventors: Dusatko, Tomas A.
• Primary Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US14/668,195
• Time in Patent Office: 419 Days
• Field of Search: 375/376, 327/156, 327/159, 331/1.R, 331/1.A, 331/18, 331/25
• US Class Current: 1/1
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03M 7/3015 Structural details of digital delta-sigma modulators
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A hybrid analog-digital, dual path, delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) that includes an integral path and a proportional path is provided. The integral path is implemented in the digital domain. The proportional path may be implemented in either the digital or analog domain. A feed-forward error correction signal generator is used to generate a feed-forward signal for attenuating in-band spurs generated by the quantization error of the integral path phase detector.

Claims

1. A dual-path, hybrid analog-digital delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) comprising:

an integral path for providing an integral path control signal, the integral path implemented in the digital domain, the integral path including an integral path phase detector;

a proportional path for providing a proportional path control signal, wherein the proportional path control signal and the integral path control signal are combined to produce a combined control signal; and

a feed-forward error correction signal generator for attenuating in-band spurs generated by quantization of a phase detector error output from the integral path phase detector, the feed-forward error correction signal generator configured to;

generate a representative signal of the instantaneous phase detector error output from the integral path phase detector by accumulating a DSM noise code sequence;

truncate the representative signal to replicate non-linearity of the integral path phase detector; and

subtract the truncated representative signal from an output of the integral path phase detector.

2. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the proportional path is implemented in the analog domain.

3. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the proportional path is implemented in the digital domain.

4. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the integral path phase detector comprises a 1-bit phase quantizer.

5. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the integral path phase detector comprises a multi-bit phase quantizer.

6. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the integral path phase detector comprises an analog phase detector.

7. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the phase detector converts an input analog phase error to a digital value.

8. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the proportional path comprises:

a proportional path phase detector; and

a proportional path loop filter coupled to an output of the proportional path phase detector;

and further wherein the integral path further comprises;

an integral path loop filter coupled to an output of the integral path phase detector; and

further wherein the hybrid analog-digital DSM based fractional-N PLL further comprises a voltage controlled oscillator (VCO) for receiving the combined control signal.

9. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1, wherein the feed-forward error correction signal generator is configured to include gain in the representative signal to account for gain variations in the phase detector due to at least one of temperature, process, and voltage.

10. A serializer-deserializer comprising the dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 1.

11. A method of correcting spurious tones in a dual-path, hybrid analog-digital delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL), the PLL including an integral path implemented in the digital domain, a proportional path, and a DSM, the integral path including an integral path phase detector, the method comprising:

generating a representative signal of the instantaneous phase detector error output from the integral path phase detector by accumulating a DSM noise code sequence;

truncating the representative signal to replicate non-linearity of the integral path phase detector; and

subtracting the truncated representative signal from an output of the phase detector.

12. A dual-path, hybrid analog-digital delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) comprising:

an integral path for providing an integral path control signal, the integral path implemented in the digital domain, the integral path including an integral path phase detector;

a proportional path for providing a proportional path control signal, wherein the proportional path control signal and the integral path control signal are combined to produce a combined control signal;

a feed-forward error correction signal generator for generating a feed-forward signal for attenuating in-band spurs generated by quantization of a phase detector error output from the integral path phase detector;

a delta sigma modulator (DSM) coupled to the feed-forward error correction signal generator; and

a fractional divider in a feedback path of the fractional-N PLL, the fractional divider having an input for receiving a control signal from the delta sigma modulator,

wherein the feed-forward error correction signal generator generates the feed forward correction signal according to the equation;

13. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the proportional path is implemented in the analog domain.

14. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the proportional path is implemented in the digital domain.

15. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the integral path phase detector comprises a 1-bit phase quantizer.

16. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the integral path phase detector comprises a multi-bit phase quantizer.

17. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the integral path phase detector comprises an analog phase detector.

18. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the phase detector converts an input analog phase error to a digital value.

19. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the proportional path comprises:

a proportional path phase detector; and

a proportional path loop filter coupled to an output of the proportional path phase detector;

and further wherein the integral path further comprises;

an integral path loop filter coupled to an output of the integral path phase detector; and

further wherein the hybrid analog-digital DSM based fractional-N PLL further comprises a voltage controlled oscillator (VCO) for receiving the combined control signal.

20. The dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12, wherein the feed-forward error correction signal includes gain to account for gain variations in the phase detector due to at least one of temperature, process, and voltage.

21. A serializer-deserializer comprising the dual-path, hybrid analog-digital DSM based fractional-N PLL of claim 12.