Floating point image sensors with different integration times
First Claim
1. An image sensor, comprising:
- an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into a plurality of tiles each of which includes multiple rows and columns of image sensor pixels;
a plurality of shutter tile column memory circuits, wherein each tile in the plurality of tiles receives bits from a selected one of the plurality of shutter tile column memory circuits; and
readout circuitry, wherein the readout circuitry is configured to read data out from a selected row of image sensor pixels that is part of a first tile in the plurality of tiles at a first point in time, and wherein the image sensor performs a reset on one other row of image sensor pixels that is part of a second tile in the plurality of tiles at a second point in time that is different than the first point in time.
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Accused Products
Abstract
An image sensor may include an array of image sensor pixels arranged in rows and columns. Each image pixel arranged along a given column may be coupled to analog-to-digital converter (ADC) circuitry that is capable of converting analog pixel signals into a floating point number. The ADC circuitry may be configured to obtain an illumination value during an auto exposure period. The illumination value, which serves as an exponent value, can be stored as tile data in respective shutter tile column memory circuits. A rolling shutter scheme may be implemented to read signals out from the array. Each tile may be allowed to integrate for a different period of time depending on the exponent value stored in the shutter tile column memory circuits. During readout, the signal generated from the ADC circuitry may represent a mantissa value that is combined with the exponent value to yield a floating point number.
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Citations
20 Claims
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1. An image sensor, comprising:
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an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into a plurality of tiles each of which includes multiple rows and columns of image sensor pixels; a plurality of shutter tile column memory circuits, wherein each tile in the plurality of tiles receives bits from a selected one of the plurality of shutter tile column memory circuits; and readout circuitry, wherein the readout circuitry is configured to read data out from a selected row of image sensor pixels that is part of a first tile in the plurality of tiles at a first point in time, and wherein the image sensor performs a reset on one other row of image sensor pixels that is part of a second tile in the plurality of tiles at a second point in time that is different than the first point in time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating an image sensor that includes an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels, the method comprising:
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with a plurality of shutter tile column memory circuits, providing bits to the array of image sensor pixels, wherein each tile in the array of image sensor pixels receives bits from a selected one of the plurality of shutter tile memory circuits; with readout circuitry, reading data out from a selected row of image sensor pixels that is part of a first tile in the array; and after reading data out from the row of image sensor pixels and before reading data out from another row, performing shutter reset on one other row of image sensor pixels that is part of a second tile in the array that is different than the first tile. - View Dependent Claims (12, 13, 14, 15)
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16. A system, comprising:
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a central processing unit; memory; input-output circuitry; and an imaging device, wherein the imaging device comprises; an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels; a first shutter tile column memory circuit that provides asserted bits to a first portion of tiles such that the first portion of tiles exhibits a first integration time; a second shutter tile column memory circuit that provides asserted bits to a second portion of tiles that is different than the first portion such that the second portion of tiles exhibits a second integration time that is different than the first integration time; and readout circuitry, wherein the readout circuitry is configured to read data out from a selected row of image sensor pixels that is part of a first tile in the array at a first time, and wherein the image sensor performs a first shutter reset on one other row of image sensor pixels that is part of a second tile in the array at a second time that is different than the first time. - View Dependent Claims (17, 18, 19, 20)
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Specification