Composite wafer semiconductor

• US 9,346,666 B2
• Filed: 08/02/2013
• Issued: 05/24/2016
• Est. Priority Date: 08/27/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Bruce C. S.
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US13/957,875
• Publication Number:
  US 20130307095A1
• Time in Patent Office: 1,026 Days
• Field of Search: 257/417, 257/777, 257/506
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/025 Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
• CPC Class Codes: B81B 7/0032 Packages or encapsulation processes for packaging MEMS B81C1/00261; packaging of smart-MEMS B81C1/0023
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface

Abstract

A composite wafer semiconductor device includes a first wafer and a second wafer. The first wafer has a first side and a second side, and the second side is substantially opposite the first side. The composite wafer semiconductor device also includes an isolation set is formed on the first side of the first wafer and a free space is etched in the isolation set. The second wafer is bonded to the isolation set. A floating structure, such as an inertia sensing device, is formed in the second wafer over the free space. In an embodiment, a surface mount pad is formed on the second side of the first wafer. Then, the floating structure is electrically coupled to the surface mount pad using a through silicon via (TSV) conductor.

Claims

1. A device comprising:

a first substrate;

a patterned first conductor layer and a first isolation set formed on a first side of the first substrate;

a patterned second conductor layer and a second isolation set formed on the first isolation set;

a free space etched in the second isolation set over a portion of the first isolation set;

a second substrate bonded to the second isolation set;

a microelectromechanical system (MEMS) device formed in the second substrate over the free space;

a first via conductor formed through the second substrate and through a portion of the second isolation set to the second conductor layer, wherein the first via conductor electrically couples the MEMS device to the second conductor layer;

a backside via formed from a second side of the first substrate to the first conductor layer;

a backside isolation layer formed on the second side of the first substrate;

a backside via conductor formed in the backside via; and

a third substrate disposed over the second substrate, wherein the third substrate is bonded to the second substrate by a first eutectic bonding material and a second eutectic bonding material.

2. The device of claim 1, wherein the first substrate comprises a semiconductive material, and wherein the second substrate comprises a conductive material.

3. The device of claim 1, wherein the second substrate is bonded to the second isolation set below approximately 500 C.

4. The device of claim 1, further comprising:

an integrated circuit (IC) formed in the first substrate.

5. The device of claim 1, wherein a portion of the second conductor layer electrically couples to a portion of the first conductor layer.

6. The device of claim 1, wherein a portion of the backside via conductor is configured as a surface mount technology (SMT) pad.

7. The device of claim 1, wherein the third substrate has a cavity formed therein that is directly over the MEMS device, and wherein the second eutectic bonding material is disposed along the third substrate within the cavity and extends directly over the MEMS device.

8. A device comprising:

a first substrate having a first surface opposing a second surface;

a first dielectric layer and a first conductive layer formed over the first surface of the first substrate;

a second dielectric layer and a second conductive layer formed over the first dielectric layer and the first conductive layer of the first substrate;

a space within the second dielectric layer;

a second substrate bonded to the second dielectric layer of the first substrate;

a floating structure formed in the second substrate over the space;

a first via extending through the second substrate and the second dielectric layer to the second conductive layer, wherein the first via electrically couples the floating structure to the second conductive layer; and

a third substrate disposed on the second substrate, wherein the third substrate is bonded to the second substrate by a eutectic system.

9. The device of claim 8, wherein the floating structure includes a microelectromechanical system (MEMS) device in the second substrate over the space.

10. The device of claim 8, wherein a portion of the first dielectric layer is exposed by the space within the second dielectric layer.

11. The device of claim 8, further comprising a second via extending through the second substrate and through a portion of the second dielectric layer.

12. The device of claim 11, wherein the second via extends to the second conductive layer.

13. The device of claim 8, wherein the first conductive layer is embedded within the first dielectric layer.

14. The device of claim 8, further comprising a bonding layer formed between the first substrate and the second substrate to facilitate bonding of the first and second substrates.

15. The device of claim 8, wherein the third substrate includes a recess formed therein directly over the floating structure, and wherein a material of the eutectic system is disposed within the recess.

16. A device comprising:

a first substrate having a first side and an opposing second side;

an isolation set on the first side of the first substrate;

a first free space disposed in the isolation set;

a second substrate coupled to the first substrate;

a floating structure disposed in the second substrate over the free space;

a first via conductor extending through the first substrate to electrically couple the floating structure to a pad on the second side of the first substrate;

a second via conductor extending through the second substrate and through a portion of the isolation set to electrically couple the floating structure to the second via conductor; and

a third substrate eutectically bonded to the second substrate, wherein the third substrate includes a second free space disposed therein, and wherein the second free space is disposed directly over the floating structure.

17. The device of claim 16, wherein the floating structure includes a microelectromechanical system (MEMS) device.

18. The device of claim 16, wherein the second substrate being coupled to the first substrate includes the second substrate physically contacting the isolation set.

19. The device of claim 16, further comprising another isolation set on the first side of the first substrate and a conductive layer embedded within the another isolation set.

20. The device of claim 19, wherein the first via conductor extends through the another isolation set on the first side of the first substrate to the conductive layer embedded within the another isolation set.