Memory centric computing
First Claim
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1. A method for processing data in a hybrid memory system, the method comprising:
- providing a hybrid memory system comprising;
a processor;
a hybrid memory buffer (HMB) module coupled to the processor, a plurality of a first memory modules coupled to the HMB module and a plurality of a second memory modules coupled to the HMB module, wherein the HMB comprises a Near-Memory-Processing (NMP) module, a memory storage controller (MSC) module coupled to the processor, and a Serializer/Deserializer (SerDes) interface coupled to the NMP module and the MSC module;
determining, by the processor, an address of a target data page from the plurality of second memory modules;
determining, by the processor, an index of a target buffer destination in an SRAM buffer provided in the NMP module;
initiating, by the processor, transfer of the target data page to the target buffer destination via writing to control and status registers provided in the MSC module; and
updating, by the processor, a data status related to the target data page and the target buffer destination in the control and status registers using the HMB module;
retrieving, by the HMB module, sixteen 4-byte data or eight 8-byte data from one or more data pages from the plurality of first or second memory modules;
combining, by the HMB module, the sixteen 4-byte data or eight 8-byte data into a single 64-byte data; and
determining, by the HMB module, an ECC (Error Correcting Code) parity for the single 64-byte data.
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Abstract
A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.
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Citations
16 Claims
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1. A method for processing data in a hybrid memory system, the method comprising:
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providing a hybrid memory system comprising; a processor;
a hybrid memory buffer (HMB) module coupled to the processor, a plurality of a first memory modules coupled to the HMB module and a plurality of a second memory modules coupled to the HMB module, wherein the HMB comprises a Near-Memory-Processing (NMP) module, a memory storage controller (MSC) module coupled to the processor, and a Serializer/Deserializer (SerDes) interface coupled to the NMP module and the MSC module;determining, by the processor, an address of a target data page from the plurality of second memory modules; determining, by the processor, an index of a target buffer destination in an SRAM buffer provided in the NMP module; initiating, by the processor, transfer of the target data page to the target buffer destination via writing to control and status registers provided in the MSC module; and updating, by the processor, a data status related to the target data page and the target buffer destination in the control and status registers using the HMB module; retrieving, by the HMB module, sixteen 4-byte data or eight 8-byte data from one or more data pages from the plurality of first or second memory modules; combining, by the HMB module, the sixteen 4-byte data or eight 8-byte data into a single 64-byte data; and determining, by the HMB module, an ECC (Error Correcting Code) parity for the single 64-byte data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for processing data in a hybrid memory system, the method comprising:
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providing a hybrid memory system comprising; a processor;
a hybrid memory buffer (HMB) module coupled to the processor, a plurality of a first memory modules coupled to the HMB module and a plurality of a second memory modules coupled to the HMB module, wherein the HMB comprises a Near-Memory-Processing (NMP) module, a memory storage controller (MSC) module coupled to the processor, and a Serializer/Deserializer (SerDes) interface coupled to the NMP module and the MSC module;determining, by the processor, an address of a target data page from the plurality of second memory modules; determining, by the processor, an index of a target buffer destination in an SRAM buffer provided in the NMP module; initiating, by the processor, transfer of the target data page to the target buffer destination via writing to control and status registers provided in the MSC module; updating, by the processor, a data status related to the target data page and the target buffer destination in the control and status registers using the HMB module; retrieving, by the HMB module, sixteen 4-byte data or eight 8-byte data from one or more data pages from the plurality of first or second memory modules; combining, by the HMB module, the sixteen 4-byte data or eight 8-byte data into a single 64-byte data; determining, by the HMB module, an ECC (Error Correcting Code) parity for the single 64-byte data; retrieving, by the HMB module, a single 64-byte data from a data page from the plurality of first or second memory modules; performing, by the HMB module, a scatter process wherein the single 64-byte data is split into data segments comprising sixteen 4-byte data or eight 8-byte data; and determining, by the HMB module, an ECC (Error Correcting Code) parity for each of the data segments. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification