Run-time code parallelization with continuous monitoring of repetitive instruction sequences
First Claim
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1. A processor, comprising:
- a processing pipeline comprising multiple hardware threads and configured to execute pre-compiled software code instructions that are stored in a memory;
multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions; and
a monitoring unit, which is configured to monitor execution of the instructions by the processing pipeline and to record, while the processing pipeline executes a sequence of the instructions, a first flow control trace traversed by the sequence and a first monitoring table indicating the registers accessed by the processing pipeline in executing the instructions in the sequence according to the first flow control trace, and which is configured to parallelize among the hardware threads of the processor, using the first monitoring table, execution of first repetitions of the sequence in accordance with the first flow control trace,wherein the monitoring unit is configured to detect, while the processing pipeline executes the sequence of the instructions, a second flow control trace traversed by the sequence, different from the first flow control trace, and to record a second monitoring table indicating the registers accessed by the processing pipeline in executing the instructions in the sequence according to the second flow control trace, and is configured to parallelize among the hardware threads of the processor, using the second monitoring table, the execution of second repetitions of the sequence in accordance with the second flow control trace,wherein the first and second monitoring tables comprise, for each register written to by the processing pipeline in executing the instructions in the sequence, a record of the last instruction in the sequence at which the processing pipeline wrote to the register.
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Abstract
A method includes, in a processor that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.
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Citations
20 Claims
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1. A processor, comprising:
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a processing pipeline comprising multiple hardware threads and configured to execute pre-compiled software code instructions that are stored in a memory; multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions; and a monitoring unit, which is configured to monitor execution of the instructions by the processing pipeline and to record, while the processing pipeline executes a sequence of the instructions, a first flow control trace traversed by the sequence and a first monitoring table indicating the registers accessed by the processing pipeline in executing the instructions in the sequence according to the first flow control trace, and which is configured to parallelize among the hardware threads of the processor, using the first monitoring table, execution of first repetitions of the sequence in accordance with the first flow control trace, wherein the monitoring unit is configured to detect, while the processing pipeline executes the sequence of the instructions, a second flow control trace traversed by the sequence, different from the first flow control trace, and to record a second monitoring table indicating the registers accessed by the processing pipeline in executing the instructions in the sequence according to the second flow control trace, and is configured to parallelize among the hardware threads of the processor, using the second monitoring table, the execution of second repetitions of the sequence in accordance with the second flow control trace, wherein the first and second monitoring tables comprise, for each register written to by the processing pipeline in executing the instructions in the sequence, a record of the last instruction in the sequence at which the processing pipeline wrote to the register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for operating a processing pipeline that includes multiple hardware threads and is configured to execute pre-compiled software code instructions that are stored in a memory while reading and writing to multiple registers during execution of the instructions, the method including:
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monitoring execution of the instructions by the processing pipeline and recording, while the processing pipeline executes a sequence of the instructions, a first flow control trace traversed by the sequence and a first monitoring table indicating the registers accessed by the processing pipeline in executing the instructions in the sequence according to the first flow control trace; parallelizing among the hardware threads of the processor, using the first monitoring table, execution of first repetitions of the sequence in accordance with the first flow control trace; while the processing pipeline executes the sequence of the instructions, detecting a second flow control trace traversed by the sequence, different from the first flow control trace; recording a second monitoring table indicating the registers accessed by the processing pipeline in executing the instructions in the sequence according to the second flow control trace; and parallelizing among the hardware threads of the processor, using the second monitoring table, the execution of second repetitions of the sequence in accordance with the second flow control trace, wherein the first and second monitoring tables comprise, for each register written to by the processing pipeline in executing the instructions in the sequence, a record of the last instruction in the sequence at which the processing pipeline wrote to the register. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification